M.V.Saideepika et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES

Vol No. 5, Issue No. 2, 255 - 260

Two phase clocked Adiabatic Logic for low

power Multiplier
M.V.Saideepika S.Karthik K.Priyadharshini
Student M.Tech VLSI Design Asst.Prof.VLSI Design Student M.Tech
SENSE,VIT University,Vellore SENSE,VIT University,Vellore SES, VIT University,Vellore
Tamil Nadu, India Tamil Nadu, India TamilNadu, India
deepikaquaser@gmail.com skarthik@vit.ac.in priyadarsinik@gmail.com

Abstract— In this paper different full adders are reviewed

based on parameters like no of transistors, power delay, and I. REVIEW ON FULL-ADDERS
aspect ratio. The different circuits are studied and evaluated
Different full adders are studied based on parameters

extensively. Among all these 8T XOR FA is the best full adder
which is more efficient which consumes less power. Different
low power methodologies of Adiabatic logics are reviewed and
the best one is implemented to 8T XOR Full Adder with low
power and high performance. This is extended to Baugh-
wooley 4 bit Multiplier
power, Aspect ratio, power delay.
ES
Keywords-component Adiabatic logic, 8T XOR FA , low
INRODUCTION
The Explosive growth in laptop, portable systems, and
cellular network has intensified the research efforts in low
power micro electronics. Addition is one of the fundamental
arithmetic operations. It is used extensively in many VLSI
systems such as application specific DSP architectures and
microprocessors In most of these systems the adder is part of
A
the critical path that determines the overall performance of the
system. That is why enhancing the performance of the 1-bit
full-adder cell (the building block of the binary adder) is a
significant goal.
In recent years, adiabatic computing has been applied to
low power systems, and several adiabatic logic families have
been proposed for low power logic applications. The energy
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number of transistors, power delay, and aspect ratio. Full
adders like Conventional CMOS Full Adder, We can also use
so many different logic based on the CMOS logic like
dynamic logic pass transistor logic and pseudo Nmos logics.
Next is Two CMOS Full Adder Based On Transmission
Function, designed by using the transmission function theory
[1] , the algebraic difficultly that the high- impedance state
cannot be expressed in Boolean algebra is overcome and the
CMOS full adder with or without driving outputs needs only
22 CMOS transistors or 16 CMOS transistors, saving 4 CMOS
transistors respectively in comparison with the two CMOS
Full adder designed in conventional method. The other FA is
Low Activity Factor Adder[2] It offers both low power and
high speed performance this FA is superior in terms of delay
and power dissipation, this is due to it’s low A.F. activity
factor and passing a strong signal in less number of pass logic.
The other FA is Bridge FA circuits these are circuits that
created a conventional conjunction between two circuits nodes
[3][4]. Using this kind of circuits the classical circuits can be
implemented faster and smaller than the conventional. The
bridge design style focused its attention to meshes and
connects each two adjacent mesh by a transistor, named
“Bridge transistor”. Bridge transistor provides the possibility
of sharing transistor of different path to create a new path from

dissipated in adiabatic circuits is considerably lesser than that
in the static CMOS circuits; hence adiabatic circuits are
promising candidates for low power circuits that can be
operated in the frequency range in which signals are digitally
processed. In this study, we compare the power consumption
in Adiabatic CMOS logic circuits and conventional CMOS
circuits.
supply lines to an output. The other full adder is static energy
recovery Full Adder[5] .The charge stored at the load
capacitance is reapplied to the control gates. The combination
of not having a direct path to ground and the reapplication
of the load charge to the control gate makes the energy
recovering full adder an energy efficient design. Finally the
other full adder is 8T XOR Full Adder. This design of
proposed full adder is based on three transistor XOR gates.

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 M.V.Saideepika et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
II OPERATION OF ADIABATIC LOGIC
A. Principle of Adiabatic circuit
The word ADIABATIC comes from a Greek word
that is used to describe thermodynamic processes that
exchange no energy with the environment and therefore, no
energy loss in the form of dissipated heat. In real-life
computing, such ideal process cannot be achieved because of
the presence of dissipative elements like resistances in a
circuit. However, one can achieve very low energy dissipation
by slowing down the speed of operation and only switching
transistors under certain conditions. The signal energies stored
in the circuit capacitances are recycled instead, of being
dissipated as heat. The adiabatic logic is also known as
ENERGY RECOVERY CMOS.
In the adiabatic switching approach, the circuit
energies are conserved rather than dissipated as heat.
Depending on the application and the system requirements,
this approach can sometimes be used to reduce the power
dissipation of the digital systems.
ES
Fig:1 circuit explaining Adiabatic switching
Here, the load capacitance is charged by a constant-current
source (instead of the constant-voltage source as in the
conventional CMOS circuits). Here, R is the resistance of the
PMOS network. A constant charging current corresponds to a
linear voltage ramp[8]. Assume, the capacitor voltage V is
C diode circuit is used, where one diode is placed between the
A
zero initially.
The voltage across the switch = IR
2
P(t) in the switch = I R
2 charges from the output node and to improve the discharging
Energy during charge = (I R)
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where, the various terms of above Equation are described as
follows:
E ― energy dissipated during charging,
Q ― charge being transferred to the load,
C ― value of the load capacitance,
R ― resistance of the MOS switch turned on,
V ― final value of the voltage at the load,
ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved.
Vol No. 5, Issue No. 2, 255 - 260
T ― time spent for charging
Now, a number of observations can be made based on
Equations as follows:
(i) The dissipated energy is smaller than for the
conventional case, if the charging time T is larger than 2RC.
That is, the dissipated energy can be made arbitrarily small by
increasing the charging time.
(ii) Also, the dissipated energy is proportional to R,
as opposed to the conventional case, where the dissipation
depends on the capacitance and the voltage swing. Thus,
reducing the on-resistance of the PMOS network will reduce
the energy dissipation.
B. Adiabatic Logic Families
Practical adiabatic families can be classified as either
Partially adiabatic or fully adiabatic. In partially adiabatic
circuit, some charge is allowed to be transferred to the ground,
while in fully adiabatic circuit ,[7] all the charge on the load
capacitance is recovered by the power supply. Fully adiabatic
T
circuits face so many problems with respect to operating speed
and input power clock synchronization. Different logic
families are Efficient Charge Recovery Logic (ECRL), 2N-
2N2P Adiabatic Logic,Positive Feedback Adiabatic Logic
(PFAL),NMOS Energy Recovery Logic (NERL), Clocked
Adiabatic Logic (CAL),True Single-Phase Adiabatic Logic
(TSEL),Source-coupled Adiabatic Logic (SCAL),Two phase
adiabatic static CMOS logic(2PASCL) and fully adiabatic
logic families are ,Pass Transistor Adiabatic Logic
(PAL),Split- Rail Charge Recovery Logic (SCRL). In this
project we are going with Two Phase Adiabatic Static CMOS
Logic(2PASCL)
C. Two Phase Adiabatic Static CMOS Logic (2PASCL):
Fig:3a,b shows a circuit diagram and waveforms
illustrating the operation of the 2PASCL inverter [8]. A two-
output node and the power clock, and the other diode is
adjacent to the nMOS logic circuit and connected to another
power source. Both the MOSFET diodes are used to recycle
speed of internal signal nodes. Such a circuit design is
particularly advantageous if the signal nodes are preceded by a
long chain of switches.
The proposed system uses a two-phase clocking split-
level sinusoidal power supply, where_  and  replaces Vdd
and Vss, respectively. One clock is in phase and the other is
inverted. The voltage level of  exceeds that of  by a factor
of Vdd/2. By using these two split-level sinusoidal
waveforms, the peak-to-peak voltage of each being 0.9 V, the
voltage difference between the current-carrying electrodes can
be minimized, and consequently power consumption can be
suppressed. The substrates of the pMOS and nMOS transistors
are connected to  and  respectively. Since the criteria for
maintaining thermal equilibrium, in which the voltage
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 M.V.Saideepika et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 255 - 260

between the current-carrying electrodes is zero when the

transistors are in the ON state [11] are satisfied, the energy
accumulated in CL is not dissipated. Results of the simulation
performed with a simulation program with the integrated
circuit emphasis circuit simulator reveal that adiabatic circuits
powered by the split-level sinusoidal consume less energy
than does a trapezoidal clock power supply, even if the rise
and fall times of the trapezoidal waveforms are set to their
maximum values. Moreover, sinusoidal waveforms can be
generated with higher energy efficiency than trapezoidal Fig: 4a 3TXOR GATE
waveforms.
The circuit operation is divided into two phases: The design of 8T full adder cell having the least number of
evaluation and hold. In the evaluation phase,  swings up transistors using 3T XOR gates is shown in Fig.5.

and  swings down. On the other hand, in the hold phase,

 swings up and  swings down.

T
ES Fig:4b 8T XOR FULL ADDER

Fig:3(a) Adiabatic Inverter

A
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Fig:6 output wave form of 8T XOR full adder

Fig:3(b)Adiabatic Inverter output wave form
E. proposed Adder is 8T XOR Full Adder:
This design of proposed full adder is based on 3T XOR. It
acquires least silicon area. The design of 3T XOR[9] gate is
shown in Fig.4. The heart of the design is based on a modified
version of a CMOS inverter and aPMOS pass transistor.
F. Applying 2PASCL to 8TXOR Full Adder:
The fig:5(a,b) shows 8TXOR Full Adder using
adiabatic logic. When compared with the normal full adder
and adiabatic full adder, adiabatic full adder’s average power
dissipation has been reduced. This simulation is done using
Eldo simulator at 180um technology.

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 M.V.Saideepika et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 255 - 260

Number of LUTs represents the area required for

implementation. The number of LUTs required in Baugh-
Wooley architecture is 28 compared to 42 in Booth multiplier
giving considerable reduction in area. Power consumption in
Baugh-Wooley multipliers is minimum compared to other
conventional multiplier units. So it clears that the signed
binary multiplication through Baugh-Wooley multiplication is
suited for the reconfigurable multiplier implementation. The
improvements in constraint can be used to make Baugh-
Wooley multiplier efficient

Fig:5(a) Adiabatic 8T XOR Full adder

T
ES Fig 6(a) Baugh wooley Multiplier

Fig:5(b) Adiabatic 8T XOR Full Adder wave form

III 4BIT MULTIPLIER USING 8T XOR FA

A
In this study, 4-bit pipelined multipliers is shown using 8T
XOR adder. Improvements in the Baugh Wooley multiplier
architecture is shown in Fig. 8.Here partial product bits
created are stored in the pipeline registers. After segregation
of partial products pipeline registers follows the positive
partial product block. This avoids the delay and the latency
caused by the two’s complement calculation. The partial
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product bits are ensured to be ready for summation at the same

time so that the errors due to latency can be removed. Latency
causes the error to be propagated to the next stages of
calculations. Pipelined registers are used to decrease the delay,
thereby improving the speed. Here the multiplier module
itself is pipelined along with the pipelined reconfigurable
structure. These bits select which multiplier functionality to be
performed in a particular time. The mode select bits are Fig 6(b) : CMOS 4-bit Multiplier
determined according to the reconfigurable regions or modules
designed.The Baugh-Wooley multiplier has increased speed
since clock period. Pipeline stages further improve the
BaughWooley architecture speed.

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 M.V.Saideepika et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 255 - 260

Fig6a : 4-BIT Multiplier wave form

The above wave form is shown for the sequence 0001 and
1001 .the same implemented for adiabatic multiplier in which
power dissipation is reduced which gives a better result.

T
Fig7(a): Adiabatic 4-bit Multiplier wave form

TABLE 1
ES circuits

Inverter
Technology
180um
Comparison table
CMOS average
power
23.4538pw
Adiabatic
average power
7.2626pw

And gate 180um 17.0780pw 10.6303pw

Nand gate 180um 7.3980pw 4.862pw

Half adder 180nm 28.8287pw 17.0780pw

Full adder 180nm 103.879w 73.248nw

A
bit 180nm 768.5405uw 235.096uw
Multiplier

V. CONCLUSION

An efficient 8T XOR Full Adder is implemented

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using CMOS and 2 phase Adiabatic static CMOS logic in

which it is extended to the Baugh Wooley Multiplier which
gives the reduced power of 30% in comparing with CMOS
logic and also transistor size is reduced so that we can reduce
silicon area.

Fig7: Adiabatic 4-bit Multiplier
REFERENCES
[1] N. Zhuang and H. Wu, “A new design of the CMOS full adder,” IEEE
J.Solid-State Circuits, vol. 27, no. 5, May 1992, pp. 840–844.
[2] E. Abu-Shama and M. Bayoumi, “A new cell for low power adders,” in
Proc.Int. Midwest Symp. Circuits Syst., 1995, pp. 1014–1017. IEEE
Circuits Devices Syst., vol. 148, Feb. 2001, pp. 19-24.

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 M.V.Saideepika et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 255 - 260

[3] Keivan Navi and Omid Kavehei, “ Low power and high performance 1-
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[6] KAUSHIK ROY, SHARAT C. PRASAD, Low-Power CMOS VLSI
Circuit Design, John Wiley & Sons, Inc, 2000.
[7] T. INDERMAUER AND M. HOROWITZ, “Evaluation of Charge
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[8] N. Anuar, Y. Takahashi and T. Sekine, “Adiabatic logic versus CMOS
for low power applications,” Proc. ITC–CSCC 2009, pp. 302–305, Jul.
[9] T.Vigneswaran, B. Mukundhan, and P. Subbarami Reddy, “A novel low
power, high speed 14 transistor RECENT ADVANCES in NETWORKING,
VLSI and SIGNAL PROCESSING ISSN: 1790-5117 275 ISBN: 978-960
474-162-5 CMOS full adeer with 50%improvement in threshold loss problem
[10]s.ka. Kawahito et al., “A 32 X 32 bit multiplier using multiple-valued mos
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M.V.Sai deepika completed her B.E in
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Electronics and communication Engineering from Adhiyamaan
college of Engineering, Hosur, Tamil Nadu State, India in 2009.
she is now Pursuing her M.Tech at VIT University, Vellore, Tamil
Nadu State, India. Her interest includes Digital Design, VLSI
Testing, and she did some good projects in the area of VLSI
Design and Testing.
A
K. Priyadarsini was born in Chennai in 1984.
She received her B.E. degree in Computer Science from Anna
University, Chennai in 2006 and she is pursuing her M.Tech in
Computer Science at VIT University, Vellore. Her area of interest
is Parallel Architecture, Software testing and Cloud computing.
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Karthik Sekhar was born in Chennai, in 1981. He received the

B.E degree from University of Madras, Chennai, in 2003 and Sathyabama
University, Chennai in 2005 and also working towardsthe PhD. Degreein MEMS.
He works as an ASSISTANT PROFESSOR at VIT University and his area of
interest includes,dynamic partial reconfiguration low power circuits and
VLSI verification and testing.

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