Lovely Professional University, Punjab

Term: 09102
Course No. CSE208 Course Title: Computer Organization and Architecture L: 4 T:0 P:0 Cr:4
Textbook: 1. Morris Mano, “Computer System Architecture”, Prentice Hall, 2007
Other specific books: 2. John P Hayes, “Computer Architecture and Organization”, Prentice Hall
3. David A Patterson, “Computer Architecture A Quantitative Approach”, Pearson Education Asia
4. P. Pal Choudhuri, Computer Organisation and Design, PHI, New Delhi, 1994 .
5. Malvino Leech, “Digital Electronics Fundamentals”
Other readings:
S.No. Journal articles as compulsory readings (Specific articles, Complete reference)
6 Journal of System Architecture, Vol 53, Number 1 to 11,2007
7 http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-823Fal -2005/LectureNotes/index.htm

8 http://www.it.uom.gr/teaching/fundamendalsofCArchitecture/materials/FOCA-Chapters-01-07-review-handout.pdf
9 http://williamstallings.com/COA5e.html
Relevant websites: (Only if relevant to the course)
S.No. Web address (Exact page address) Salient Features
10 http://www.rocw.raifoundation.org/computing/BCA/computerarchitecture Better explanation of Micro programmed
/lecture-notes/lecture-29.pdf vs hardwired control unit
11 http://www.stanford.edu/class/cs110/handouts/13_Addressing_Modes.p Describes addressing modes with
df examples
12 http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer- Open Courseware
Science/6-823Fall-2005/LectureNotes/index.htm
13 http://www.cseiq.org/pdf_files/1233047339_computer%20architecture.pdf Computer Architecture

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 Detailed Plan for Lectures
Week No. Lecture Topic Chapters/ Homework to be Pedagogical Pedagogical tool Date Delivered2
No. Sections of assigned to tool Demonstration/ case
(Mention Regular
Textbook/ other students 3 Demonstratio study/ images/
(R) / Make Up (M)
reference1 3 n/ case animations
class)
study/ etc.actually used
images/
animations
etc.planned4
Part 1 (one fourth of total number of lectures)
1 1 Review of Number System: 1,Ch 3 Homework 1

Binary, Hexadecimal, & Sec 3.1,3.4

Octal No. System,
Conversion from one number
system to another. Need of
Number Systems, Integer &
Floating Point Numbers
1 2 Overview of Codes – Gray 1, Ch 3 Homework 1
Code, BCD, Excess, Sec 3.5
ASCII
1 3 Representation of 1, Ch 3 Homework 1
Integers(Signed Sec 3.2
Magnitude, 1s & 2s
Complement)
1 4 Real numbers ( Fixed point & 1, Ch 3 Homework 1
Floating Point Sec 3.3,3.4
representation)
2 5 Complements , (r-1)’s and r 1, Ch 3 Homework 1
complement, addition and Sec 3.2
subtraction of binary and
2
 decimal numbers
2 6 Basics of Digital Electronics, 1, Ch 1 Homework 1
Codes, Logic Gates, Sec 1.1,1.2
Combinational Circuits
2 7 Flip Flops – SR, JK, T, D, 1, Ch 1 Homework 1
Master Slave, Edge Sec 1.6
triggered flip flops,
Excitation tables
2 8 Registers, Registers with 1, Ch 2 Homework 1
parallel Load, Shift DOA 1
Sec 2.4,2.5
registers, bidirectional
shift register with parallel
load
3 9 Counters, Binary Counters, 1, Ch 2 Homework 1
synchronous binary Sec 2.6
counters, applications
3 10 Multiplexers and 1, Ch 2 Homework 1
Demultiplexers, 2n – 1 Sec 2.2,2.3
line multiplexer and
function tables.
Decoders, NAND gate
decoder, Decoder
Expansion, Encoder
Applications
3 11 Concept of Registers in a 1, Ch 5 Homework 1
CPU, Purpose of Sec 5.2
registers, word length,
3 12 Generally used registers in a 1, Ch 5 Homework 1
CPU & their purpose Sec 5.2
4 13 Program counter, Instruction 1, Ch 5 Homework 2

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 register, Stack Pointer, Sec 5.2
Data Register, Address
registers etc. Common
Bus System, Connection
of basic computer
registers to common bus
4 14 Concept of Micro-operation, 1, Ch 5 Homework 2
Instruction Code, and Sec 5.3
Instruction set., Types of
instructions and
instruction formats,
Instruction set
completeness
Part 2 ( another one fourth of total number of
lectures)
4 15 Conventions used to 1, Ch 4 Homework 2
represent micro- Sec 4.5
operations, Register
Transfer language,
Register Transfer, control
function, basic symbols
for register transfers
4 16 how operations involving 1, Ch 4 Homework 2
registers & memory are DOA 2
represented, bus and
memory transfer, bus DOS-DOT1
sytem using multiplexers,
bus selection
5 17 Three state bus buffers, 1, Ch 4 Homework 2
memory transfer, memory Sec 4.3
read, memory write
5 18 Concept of Data Bus, 1, Ch 4 Homework 2

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 Address Bus & Control
Bus, Effects of buses on
the performance of a
system
5 19 Instruction cycle, fetching 1, Ch 5 Homework 2
and decoding, register Sec 5.5
transfer for the fetch
phase. Determining the
type of instruction , flow
chart for instruction cycle
5 20 Execution of register 1, Ch 5 Homework 2
reference instructions- Sec 5.5
CLA, CLE, CMA, CME,
CIR, CIL, INC, SPA,
SNA, SZA, SZE, HLT
6 21 Execution of memory 1, Ch 5
reference instructions-
AND, ADD, LDA, STA,
BUN, BSA, ISZ
6 22 General Register 1, Ch 5
Organization, control Sec 5.6
word, ALU, examples of
micro operations
6 23 Instruction formats, single 1, Ch 8
accumulator, general
Sec 8.4
register and stack
organization, Three and
two address instructions.
One, zero address and
RISC instructions,
examples
6 24 Addressing modes- 1, Ch 8 DOS-DOT2

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 immediate, impled, Sec 8.5
register, register indirect,
direct address, indirect
address, relative
addressing modes. Auto
increment and auto
decrement, indexed
addressing modes, base
register, a numeric
example. Control unit of a
basic computer, timing
signals, an example of
control timing signal
MID-TERM
Part 3 (another one fourth of total number of
lectures)
7 25 Hardwired vs micro 1, Ch 7 Homework 3
programmed control Sec 7.2,
7.3

7 26 control memory 1, Ch 7 Homework 3

Sec 7.3
7 27 Stack organization: LIFO, 1, Ch 8 Homework 3
Stack pointer
Sec 8.3
7 28 register stack,memory stack 1, Ch 8 Homework 3
Sec 8.3 DOA 3
8 29 Operations on stacks – 1, Ch 8 Homework 3
Push, Pop Sec 8.3
8 30 sequence of micro 1, Ch 8 Homework 3

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 operations in register
stack, memory stack
8 31 Reverse polish notation, 1, Ch 8 Homework 3
conversion to RPN Sec 8.3
8 32 evaluation of arithmetic 1, Ch 8 Homework 3
operation Sec 8.3
9 33 stack operations 1, Ch 8 Homework 4
Sec 8.3
9 34 Program interrupt, types of 1, Ch 8 Homework 4
interrupts- Sec 8.7
9 35 external, internal and software, 1, Ch 8 Homework 4
examples Sec 8.7
9 36 Interrupt cycle 1, Ch 5 Homework 4
Sec 8.7 DOA 4
DOS-DOT3
10 37 Reduced instruction set 1, Ch 8 Homework 4
computing, characteristics Sec 8.8
10 38 Complex instruction set 1, Ch 8 Homework 4
computing, characterstics Sec 8.8
10 39 RISC vs CISC, examples 1, Ch 8 Homework 5
Sec 8.8
10 40 Peripheral devices – monitor, 1,Ch 11 Homework 5
printer, keyboard, ASCII DOA-5
Sec 11.1
characters
DOS-4/DOT-4

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 Part 4 (another one fourth of total number of
lectures)
11 41 I/O interface 1, Ch 11 Homework 5
sec 11.2
11 42 IO vs memory bus 1, Ch 11 Homework 5
sec 11.2
11 43 Isolated vs memory mapped 1, Ch 11 Homework 5
I/O sec 11.2
11 44 IOP, CPU- IOP 1, Ch 11 Homework 5
communication sec 11.2
12 45 Memory hierarchy 1, Ch 12 Homework 5
sec 12.1

12 46 main memory, auxiliary 1, Ch 12 Homework 5

memory, cache memory Sec 12.3
12 47 Magnetic disks and magnetic 1, Ch 12 DOS-
tapes 5/DOT-5
Sec 12.3
12 48 Brief introduction to cache 1, Ch 12
and virtual memory Sec
2.5,12.6
SpillOver(2xL)

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 Details of Homework and Case Studies Planned:
Homework Topics of the homework Nature of Homework Actual Actual Actual date of
No. (Group/individual/fieldwork) DoA5 DoS6 & of task
DoT7 evaluation
1 Number System and representation of numbers, INDIVIDUAL
Designing using basic digital electronics,
Basic Register Organization
2 Common bus systems ,CPU buses and bus INDIVIDUAL
Transfer , Instruction Cycle, Instruction
formats

3 Stack Organiation,Operations on stack INDIVIDUAL

4 RISC,CISC ,Interrupts INDIVIDUAL

Scheme for CA: (out of 100)

Component Frequency Marks for each Total Marks
Homework based tests/quizzes 4 best 25 100
of 5
Term paper NA
Lab performance (only if there is a lab component) NA
Any other: specify
Total 100

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List of suggested topics for term paper [at least 15] (Student to spend about 15 hrs on any one specified term paper)
S.No. Topic
1
NA

15

Plan for Tutorials: (Plan for 7 x T before MTE , 6 x T after MTE)(Please do not use these time slots for syllabus coverage)
S. No. Topic (s) Type of pedagogical Pedagogical tool Date held for Date held
tool(s) planned actually used – group A. for group B
(case analysis, mention the title.
problem solving, (case analysis,
test, role play, problem solving,
business game etc) test, role play,
business game)
NA

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Prepared by (Instruction Planner: Name, signature & date)

Comments of Coordinator of Specialisation (COS) wherever this designation exists/ CoD-F (if any)
Signature & Date

Comments of HoD-F / HOF (if there is no HOD-F)

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