AIM: Write a verilog program for Half adder using structural modelling

style

NAME: Ankita Goel

ENROLLMENT NO.: 070126
TOOL USED: Active HDL

Program
module halfadder (a, b, sum, carry);
input a, b;
output sum, carry;
xor x1 (sum, a,b);
and a1(carry,a,b);
endmodule

Waveform
AIM: Write a verilog program for Half adder using Dataflow modeling
style

NAME: Ankita Goel

ENROLLMENT NO.: 070126
TOOL USED: Active HDl

Program
module halfadder (a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

Waveform
AIM: Write a verilog program for Half adder using Behavioural modeling
style

NAME: Sonam Singhal

ENROLLMENT NO.: 070050
TOOL USED: Tanner EDA

Program
module halfadder (a,b,sum,carry);
input a,b;
output sum,carry;
reg sum,carry;
always @(a or b)
begin
sum=a^b;
carry=a&b;
end
endmodule

Waveform
AIM: Write a verilog program for Full adder using mixed modeling style

NAME: Ankita Goel

ENROLLMENT NO.: 070126
TOOL USED: Active hdl

Program

module fulla (a,b,c,sum,carry);

input a,b,c;
output sum,carry;
wire w1;
xor x1 (w1,a,b);
assign sum=w1^c;
reg t1,t2,t3,carry;
always @ (a or b or c)
begin
t1= a&b;
t2= b&c;
t3= c&a;
carry= t1|t2|t3;
end
endmodule

Waveform
AIM: Write a verilog program for 4:1 multiplexer using conditional
statement

NAME: Ankita Goel

ENROLLMENT NO.: 070126
TOOL USED: Active Hdl

Program
module mux (i0,i1,i2,i3,s0,s1,y);
input i0,i1,i2,i3,s0,s1;
output y;
assign y= s1?(s0?i3:i2):(s0?i1:i0);
endmodule

Waveform
AIM: Write a verilog program for a CMOS inverter using switch
statement

NAME: Ankita Goel

ENROLLMENT NO.: 070126
TOOL USED: Active Hdl

Program
module switchin (in,out);
input in;
output out;
supply1 vdd;
supply0 gnd;
pmos (out,vdd,in);
nmos(out,gnd,in);
endmodule

Waveform