Design, Applications and Discussions on VLSI

Muhammad Fahd Waseem

Faculty of Electronics Engineering
Ghulam Ishaq Khan Institute of Engineering Sciences and Technology
Topi, Swabi, Pakistan
Email: muhammadfahd@ieee.org

Abstract—This is originally a course assignment done for the

CS465 course at the GIK Institute, Pakistan, and was completed
on the 17th of November, 2010. This is NOT a research paper,
though every attempt has been made to keep the information
in this document as accurate as possible. This paper is released
under the Creative Commons Share-Alike license only.
This paper answers some simple questions that rise in de-
velopment and design of ASICs, and VLSI, on the logic and
physical level. It does so by solving some small problems in
an optimized manner. A discourse on the tools used, and the
techniques employed in such endeavours is also provided.
Index Terms—ASIC, VLSI, MicroWind, Switch Level, Physical
Level, EDA, routing

I. I NTRODUCTION
Four questions are answered in this VLSI and ASIC Design
Course Assignment.
1) To draw and simulate the optimized physical level layout
of the logic expression
(A + B) · (B + C)
using "µwind" (MicroWind) as the graphical layout
software tool.
2) To draw and simulate the optimized physical level layout
of a single-bit full-adder for inputs A, B and Cin and
outputs S and Cout .
3) A discussion of commercially available CAD tools
which are used in real time chip designing for logic
Figure 1. OAI implemented CMOS Schematic for Question 1
verification, net-list generation (synthesis tools), logic
level simulators and physical level simulators.
4) A discussion on interconnect routing techniques and
methods in physical layouts. It may be seen from the layout that care has been taken
The sections that follow answer the questions in detail, in to keep the overall size of the layout at a minimum, while
the same order. Some basic level of knowledge in VLSI & also maintaining the mimimum number of contacts (vias) and
ASICs is required to be able to understand them completely[1]. length of the electrical routes as short as possible. The layout
is compliant with the standard design rules, and was subject
II. Q UESTION 1 to DRC checks before finalization.
A. Answer Explanation Table I shows the expected results from the evaluation of
The given expression is: the given expression. Fig. 3. shows the MicroWind simulation
results.
F = (A + B) · (B + C)
This can easily be implemented efficiently using the OAI
(Or-And-Invert) method for implementing CMOS circuits. See B. Conclusion to Question 1
Fig. 1.
Fig. 2. shows the optimized physical layout design. Note The physical layout is as optimized as possible, and the
that the physical layout diagram has been converted into simulation results match the expected results of the given logic
sketchmark patterns for printing clarity. expression.
 Figure 3. Simulation Verification for Question 1

Table I
E XPECTED S IMULATION R ESULTS FOR Q UESTION 1

A B C Output
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

III. Q UESTION 2
A. Transmission Gate Based Full Adder
A single-bit full-adder can be implemented using the equa-
tions:
S = A ⊕ B ⊕ Cin
Cout = (A · B) + (Cin · (A ⊕ B))
Note that the + operator in the expression for Cin can be
replaced by ⊕ without altering the logic of the circuit, as
shown in Table II, our design will become far simpler because
we now have to construct only two types of gates: XOR &
AND. Cout = (A·B)⊕(Cin ·(A⊕B)). These can be replicated
Figure 2. CMOS Physical Layout Schematic for Question 1 in cells. See Fig. 4.
However, using this approach increases the number of
gates involved. As the assignment question explicitly asks for
 Table II
E XPECTED R ESULTS AND E QUATION O UTPUT FOR Q UESTION 2

Cout =
Cin B A S = A ⊕ B ⊕ Cin
(A·B)⊕(Cin ·(A⊕B))
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Figure 6. TG Based Full Adder with 24 Transistors

Figure 4. Gate Implementation of Single-Bit Full-Adder with XOR & AND

optimized layouts, the least size solution demands that the use
of the OR gate be maintained.
For the XOR gates, a particularly compact configuration
utilizing transmission gates (TG) may be used. Fig. 5. shows
such a XOR gate. A full adder implemented using this is the Figure 7. Basic / Unmanipulated Mirror Adder
TG XOR gated adder. A TG XOR gated adder can be imple-
mented in a minimum of 26 transistors. This is less transistors
than the standard OR & AND full adder implementation. ration is actually more than that used in the TG XOR gated
Finally, there is another TG based full adder that uses just 24 adder, while still less than the standard OR & AND full adder.
transistors, as shown in Fig. 6, however the routing complexity However, the basic mirror adder, as shown in Fig. 7. uses
is high. the expressions below[2]:

B. Mirror Adders Co = AB + Ci A + Ci B, Cout = Co

There is another method for designing a CMOS single-bit
full-adder: the mirror adder. This is a nmos-pmos symmetric
structure, and the number of transistors used in this configu-
Figure 5. TG XOR Gate
S = ABCi + Co A + Co B + Co Ci , Cin = Ci
These equations can further be manipulated for true-
mirroring i.e. such that the upper and lower half are truly
symmetric. The following sets of equations are the same in
logic, yet lend themselves to true nmos-pmos symmetry:
Co = AB + Ci · (A + B)
Co = (A + B) · (Ci + AB)
&
S = (A + B + Ci ).Co + ABCi
S = (ABCi + Co ) · (A + B + Ci )
Note in particular the re-usage of the Co in both the S
equations. In each set, one equation forms the nmos circuit,
while the other equation forms the pmos circuit. Also note that
the equations are essentially the same with all the operators
reversed. Fig. 8. shows the implementation.

Figure 8. True Mirror Adder
C. Physical Layout Selection and Simulation
Due to the ease of implementation, and size efficiency
of the true-symmetry mirror adder, that is the one chosen
for the physical layout. The physical layout so developed in
MicroWind is shown in Fig. 9. The simulation of this layout,
also done in MicroWind, is shown in Fig. 10.
D. Conclusion to Question 2
After considering multiple designs and techniques, it was
deemed that the true-symmetry mirror adder was the best one
for our requirements. It was highly optimized, and simulation
was working perfectly.
IV. Q UESTION 3
A. Introduction
The tools being referenced are known as ECAD (Electronic
Computer Aided Design). They are also often known as EDA
(Electronic Design Automation) tools.
These days, the EDA tools available are usually highly
modular, and often perform more than one particular task.
They also come in a wide range of prices: completely free,
free just for academic use, low cost, or high cost. Naturally,
the high cost tools are generally better in terms of functional
capability and performance, particularly for large circuits.
Due to this variance, it is no longer possible to distinctly
categorize most software tools as logic verification tools,
net-list generation (synthesis tools), logic level simulators,
physical level simulators or anything such.
Logic verification means the confirmation of the correct
working for given circuit design. Synthesis tools generate a
net-list for inter-component connections that can be exported
to implementation tools. Logic level simulators simulate the
digital logic of a circuit; physical level simulators, likewise,
simulate the actual physical layouts.
Commercially, a few companies dominate the industry.
These companies follow industrial standards, and have estab-
lished their own softwares as standards as well. It should be
noted that the software these companies produce is geared
towards volume or high-budgeted manufacturers, and is gener-
ally priced accordingly. Another point to note is that the Linux
platform is prevalent in the high performance semiconductor
industry as an OS, so most of the products provided by these
companies usually do not run on the Microsoft Windows© OS.
The following are the major EDA software companies:
• Synopsys
• Cadence
• Mentor Graphics
• Magma Design Automation
• Zuken Inc. (This company, however, provides no software
tools for IC level EDA.)
• EEsof, Agilent Technologies EDA Arm
Of these, Synopsys and Cadence have the largest market
caps.
B. Synopsys[3]
The Discovery Verification Platform is an integrated port-
folio of functional, formal, low-power and hardware-assisted
verification tools. Discovery provides high performance, high
accuracy and efficient interactions among best-in-class tech-
nologies including mixed-HDL simulation, mixed-signal simu-
lation, assertions, coverage, testbench automation, verification
IP, formal analysis, unified debug, equivalence checking and
rapid prototyping.
Synopsys also provides a large portfolio of tools for syn-
thesis.
C. Cadence[4]
The Virtuoso Platform is a set of tools for designing full-
custom integrated circuits; it includes schematic entry, behav-
ioral modeling (Verilog-AMS), circuit simulation, full custom
layout, physical verification, extraction and back-annotation. It
is used mainly for analog, mixed-signal, RF, and standard-cell
designs, but also memory and FPGA designs.
The Encounter Platform is a set of tools for creation of dig-
ital integrated circuits. This includes floorplanning, synthesis,
test, and place and route. Typically, a digital design starts from
Verilog netlists.
The Incisive Platform is a set of tools for simulation and
functional verification of RTL including Verilog, VHDL and
SystemC based models. This includes formal verification,
formal equivalence checking, hardware acceleration, and em-
ulation.
D. Mentor Graphics[5]
Most pertinent for our purposes is the Questa ADMS
(Analog-Digital Mixed Signal Simulator). It gives design-
ers a comprehensive environment for verifying complex
analog/mixed-signal (AMS) System-on-Chip (SoC) designs.
ADMS combines four high performance simulation engines in
one efficient tool: Eldo for general purpose analog simulations,
Questa for digital simulations and ADiT for fast transistor-
level simulations.
That in itself is a subpart of the Mentor Graphics IC-Flow
or ICStudio platform. This platform encompasses the complete
IC development flow, from design to production mask layouts.
 Figure 9. True Mirror Adder Physical Layout in CMOS

Figure 10. Single-Bit Full-Adder Simulation for Question 2 Mirror Adder

E. Magma Design Automation[6] 4) Special Signals: Non standard width, differential pairs,
The Talus Suite provides digital chip implementation tools, shielded, etc.
while the Titan Suite provides analog/mixed-signal design 5) General Routing: The remainder of the signals.
tools for ICs. For the items 3-5, meshes are generally used in large circuits.
These are two dedicated layers of straight paths, perpendicular
F. EEsof, Agilent Technologies EDA Arm[7] to each other. These meshes can have the ‘links’ broken at the
Integrated Circuit Characterization and Analysis Program right places to create connections.
(IC-CAP) is a tool for DC and RF semiconductor device mod- One final twist to this scheme comes as better fabrication
eling. IC-CAP extracts accurate compact models used in high processes reduce cell sizes significantly. Some designers now
speed/digital, analog and power RF applications. IC-CAP is use semiconductor layer components to provide main signal
used for modeling silicon CMOS, bipolar, compound gallium paths, or even use full gate sized semiconductor logic features
arsenide (GaAs), gallium nitride (GaN) and many other device for signal crossing using XOR gates[9].
technologies. IC-CAP is the advanced, customizable modeling C. Conclusion
software and includes measurement, simulation, optimization
and statistical analysis tools. Interconnect routing is a vast area of work, and cannot as
such be answered in such short space as this. However, the
V. Q UESTION 4 vital points were provided.
A. Interconnect Routing Consideration ACKNOWLEDGMENT
Metal or wire interconnects between semiconductor features The author would like to thank his teachers, instructors
are an essential part of VLSI design. Optimized interconnec- and TAs without whom this work would neither have been
tions will cause better signal fidelity, low signal latency, lower required, nor completed.
costs and greater packing density. These come in the shape of
minimum number of vias, shortest possible routes, decreased R EFERENCES
capacitances, least number of layers and best placement of [1] J. P. Uyemura, Introduction to VLSI Circuits and Systems. Georgia
Instiute of Technology, USA: Chinese Press, 2001.
features. [2] (2010, Nov) Vlsi principles. University of
California, Santa Barbara. [Online]. Available:
B. Interconnect Routing Techniques and Methods http://www.ece.ucsb.edu/courses/ECE124/124A_F05Banerjee/Lectures/
Lecture16.pdf
Perhaps the best example of optimized interconnects comes [3] (2010, Nov) Synopsys.com. Synopsys, Inc. [Online]. Available:
from Cadence’s Encounter Platform[4]. It includes options http://www.synopsys.com/
to ‘Place and Route’ semiconductor features as optimally as [4] (2010, Nov) Cadence design systems. Cadence Design Systems, Inc.
[Online]. Available: http://www.cadence.com/us/pages/default.aspx
possible when provided a Verilog netlist. It takes into account [5] (2010, Nov) The eda technology leader - mentor graphics. Mentor
given design rules when doing so, as well as user specified Graphics® . [Online]. Available: http://www.mentor.com/
weights to the typical routing tradeoffs: numbers of vias, [6] (2010, Nov) Magma: Integrating digital & analog ic design & verification.
Magma Design Automation. [Online]. Available: http://www.magma-
layers, route lengths etc. This is an example of letting an EDA da.com/
tool do ‘PAR’. Else, these must be done manually. [7] (2010, Nov) Agilent eesof eda design & simula-
Other methods for interconnect routing optimization come tion software - agilent. Agilent Technologies, Inc. [On-
line]. Available: http://www.home.agilent.com/agilent/product.jspx?
from the fabrication process itself. Better materials and diver- cc=US&lc=eng&ckey =1475688& nid=-34360.0.00&id=1475688
sion from the typical 90˚ ‘Manhattan’ layout promise far better [8] D. Clein, CMOS IC layout: concepts, methodologies,
interconnect routing possibilities and far denser packaging at and tools. Newnes, 2000, no. 1. [Online]. Available:
http://books.google.com/books?id=fzuX6tyIeBkC
the price of increased cost. [9] (2010, Nov) Xor gate - wikipedia, the free ency-
Typically, there need to be specially optimized routes be- clopedia. WikiMedia Foundation, Inc. [Online]. Available:
tween blocks for[8] for the given purposes. They are also http://en.wikipedia.org/wiki/XOR_gate
generally handled in this order.
1) Power supplies: High current and connectivity; need
to be connected to almost all transistors. These are
typically placed in ‘straps’ rows of high large width lines
with smaller columnar paths to the transistor blocks.
The straps originate at the power source. One layer
is generally completely reserved for power in larger
designs.
2) Clocks: Pervasive, and dynamic. These may be supplied
like the power lines, or alternatively they may be ‘tree-
d’, i.e. buffered at strategic points, with thinning path
widths from there on.
3) Buses: Groups of signals. Generally critical.