ADDERS AND SUBTRACTORS Behavioral Modeling:

AIM: library IEEE;

To develop the source code for adders and subtractors by use IEEE.STD_LOGIC_1164.ALL;
using VHDL/VERILOG and obtain the simulation, use IEEE.STD_LOGIC_ARITH.ALL;
synthesis, place and route and implement into FPGA. use IEEE.STD_LOGIC_UNSIGNED.ALL;
ALGORITM: entity haddbehavioral is
Step1: Define the specifications and initialize the design. Port ( a : in std_logic;
Step2: Declare the name of the entity and architecture by b : in std_logic;
using VHDL source code. sum : out std_logic;
Step3: Write the source code in VERILOG. carry : out std_logic);
Step4: Check the syntax and debug the errors if found, end haddbehavioral;
obtain the synthesis report. architecture Behavioral of haddbehavioral is
Step5: Verify the output by simulating the source code. begin
Step6: Write all possible combinations of input using the p1:process (a,b)
test bench. begin
Step7: Obtain the place and route report. sum<= a xor b;
BASIC ADDERS & SUBTRACTORS: carry<= a and b;
end process p1;
HALF ADDER: end Behavioral;

Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddstructural is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddstructural;
architecture structural of haddstructural is
component xor2
LOGIC DIAGRAM port(a,b:instd_logic;
z:out std_logic);
VHDL SOURCE CODE: end component;
--Design : HALF ADDER component and2
port(a,b:instd_logic;
Dataflow Modeling: z:out std_logic);
library IEEE; end component;
use IEEE.STD_LOGIC_1164.ALL; begin
use IEEE.STD_LOGIC_ARITH.ALL; x1: xor2 port map (a,b,sum);
use IEEE.STD_LOGIC_UNSIGNED.ALL; a1: and2 port map (a,b,carry);
entity hadd is end structural;
Port ( a : in std_logic;
b : in std_logic; and2 component source code:
sum : out std_logic; library IEEE;
carry : out std_logic); use IEEE.STD_LOGIC_1164.ALL;
end hadd; use IEEE.STD_LOGIC_ARITH.ALL;
architecture dataflow of hadd is use IEEE.STD_LOGIC_UNSIGNED.ALL;
begin entity and2 is
sum <= a xor b; Port ( a : in std_logic;
carry <= a and b; b : in std_logic;
end dataflow; z : out std_logic);
end and2;
architecture dataflow of and2 is
begin Port ( a : in std_logic;
z<= a and b; b : in std_logic;
end dataflow; diff : out std_logic;
borrow : out std_logic);
xor2 component source code: end hsub_behv;
library IEEE; architecture Behavioral of hsub_behv is
use IEEE.STD_LOGIC_1164.ALL; begin
use IEEE.STD_LOGIC_ARITH.ALL; p1:process(a,b)
use IEEE.STD_LOGIC_UNSIGNED.ALL; variable abar:std_logic;
entity xor2 is begin
Port ( a : in std_logic; abar:= not a;
b : in std_logic; diff<=a xor b;
z : out std_logic); borrow<=abar and b;
end xor2; end process p1;
architecture dataflow of xor2 is end Behavioral;
begin
z<= a xor b; Structural Modeling:
end dataflow; library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
HALF SUBSTRACTOR: use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_structural is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_structural;
architecture structural of hsub_structural is
component xor2
port(a,b:instd_logic;
LOGIC DIAGRAM z:out std_logic);
end component;
VHDL SOURCE CODE: component and2
port(a,b:instd_logic;
Dataflow Modeling: z:out std_logic);
library IEEE; end component;
use IEEE.STD_LOGIC_1164.ALL; component not1
use IEEE.STD_LOGIC_ARITH.ALL; port(a:instd_logic;
use IEEE.STD_LOGIC_UNSIGNED.ALL; z:out std_logic);
entity hsub_dataflow is end component;
Port ( a : in std_logic; signal abar:std_logic;
b : in std_logic; beginx1:xor2 port map (a,b,diff);
diff : out std_logic; a1:and2 port map (abar,b,borrow);
borrow : out std_logic); n1:not1 port map (a,abar);
end hsub_dataflow; end structural;
architecture dataflow of hsub_dataflowisbegin
diff <= a xor b; and2 component source code:
borrow <= not a and b; library IEEE;
end dataflow; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Behavioral Modeling: use IEEE.STD_LOGIC_UNSIGNED.ALL;
library IEEE; entity and2 is
use IEEE.STD_LOGIC_1164.ALL; Port ( a : in std_logic;
use IEEE.STD_LOGIC_ARITH.ALL; b : in std_logic;
use IEEE.STD_LOGIC_UNSIGNED.ALL; z : out std_logic);
entity hsub_behv is end and2;
architecture dataflow of and2 is
begin
z<= a and b;
end dataflow;
xor2 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;
not1 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;
FULL ADDER:
LOGIC DIAGRAM:
VHDL SOURCE CODE:
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_dataflow is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_dataflow;
architecture dataflow of fadd_dataflow is
signal p,q,r,s:std_logic;
begin
p<= a xor b;
q<= a and b;
r<= b and c;
s<= c and a;
sum<= p xor c;
carry<= q or r or s;
end dataflow;
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_behv;
architecture Behavioral of fsub_behv is
begin
p1:process(a,b,c)
variable abar,r,s,t:std_logic;
begin
abar:=not a;
r:=abar and b;
s:=b and c;
t:=c and abar;
diff<=a xor b xor c;
borrow<=r or s or t;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_structural;
architecture structural of fsub_structural is
component xor2
port(a,b:instd_logic;
z:out std_logic);
end component;
component and2 library IEEE;
port(a,b:instd_logic; use IEEE.STD_LOGIC_1164.ALL;
z:out std_logic); use IEEE.STD_LOGIC_ARITH.ALL;
end component; use IEEE.STD_LOGIC_UNSIGNED.ALL;
component not1 entity xor2 is
port(a:instd_logic; Port ( a : in std_logic;
z:out std_logic); b : in std_logic;
end component; z : out std_logic);
component or3 end xor2;
port(a,b,c:instd_logic; architecture dataflow of xor2 is
z:out std_logic); begin
end component; z<= a xor b;
signal p,q,r,s,abar:std_logic; end dataflow;
begin
x1:xor2 port map (a,b,p); FULL SUBSTRACTOR:
x2:xor2 port map (p,c,diff); LOGIC DIAGRAM:
n1:not1 port map (a,abar);
a1:and2 port map (abar,b,q);
a2:and2 port map (b,c,r);
a3:and2 port map (c,abar,s);
o1:or3 port map (q,r,s,borrow);
end structural;

and2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic; VHDL SOURCE CODE:
z : out std_logic);
end and2; Dataflow Modeling:
architecture dataflow of and2 is library IEEE;
begin use IEEE.STD_LOGIC_1164.ALL;
z<= a and b; use IEEE.STD_LOGIC_ARITH.ALL;
end dataflow; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_dataflow is
or3 component source code: Port ( a : in std_logic;
library IEEE; b : in std_logic;
use IEEE.STD_LOGIC_1164.ALL; c : in std_logic;
use IEEE.STD_LOGIC_ARITH.ALL; diff : out std_logic;
use IEEE.STD_LOGIC_UNSIGNED.ALL; borrow : out std_logic);
entity or3 is end fsub_dataflow;
Port ( a : in std_logic; architecture dataflow of fsub_dataflow is
b : in std_logic; signal abar:std_logic;
c : in std_logic; begin
z : out std_logic); abar<=not a;
end or3; diff<=a xor b xor c;
architecture dataflow of or3 is borrow<=(abar and b) or (b and c) or (c and abar);
begin end dataflow;
z<= a or b or c;
end dataflow; Behavioral Modeling:
library IEEE;
xor2 component source code: use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; a1:and2 port map (abar,b,q);
use IEEE.STD_LOGIC_UNSIGNED.ALL; a2:and2 port map (b,c,r);
entity fsub_behv is a3:and2 port map (c,abar,s);
Port ( a : in std_logic; o1:or3 port map (q,r,s,borrow);
b : in std_logic; end structural;
c : in std_logic;
diff : out std_logic; ENCODERS AND DECODERS
borrow : out std_logic); AIM
end fsub_behv; To develop the source code for encoders and decoders
architecture Behavioral of fsub_behv is by using VHDL/VERILOG and obtain the
beginp1:process(a,b,c) simulation, synthesis, place and route and implement
variable abar,r,s,t:std_logic; into FPGA.
begin ALGORITHM
abar:=not a; Step1: Define the specifications and initialize the design.
r:=abar and b; Step2: Declare the name of the entity and architecture by
s:=b and c; using VHDL source code.
t:=c and abar; Step3: Write the source code in VERILOG.
diff<=a xor b xor c; Step4: Check the syntax and debug the errors if found,
borrow<=r or s or t; obtain the synthesis report.
end process p1; Step5: Verify the output by simulating the source code.
end Behavioral; Step6: Write all possible combinations of input using the
test bench.
Structural Modeling: Step7: Obtain the place and route report.
library IEEE; ENCODER
use IEEE.STD_LOGIC_1164.ALL; LOGIC DIAGRAM TRUTH TABLE:
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_structural;
architecture structural of fsub_structural is
component xor2
port(a,b:instd_logic;
z:out std_logic);
end component;
component and2
port(a,b:instd_logic;
z:out std_logic);
end component;
component not1
port(a:instd_logic; VHDL SOURCE CODE
z:out std_logic); Dataflow Modeling:
end component; library IEEE;
component or3 use IEEE.STD_LOGIC_1164.ALL;
port(a,b,c:instd_logic; use IEEE.STD_LOGIC_ARITH.ALL;
z:out std_logic); use IEEE.STD_LOGIC_UNSIGNED.ALL;
end component; entity encoder_dataflow is
signal p,q,r,s,abar:std_logic; Port ( d : in std_logic_vector(7 downto 0);
begin z : out std_logic_vector(2 downto 0));
x1:xor2 port map (a,b,p); end encoder_dataflow;
x2:xor2 port map (p,c,diff); architecture dataflow of encoder_dataflow is
n1:not1 port map (a,abar); begin
z(2)<= d(4) or d(5) or d(6) or d(7); or4 component source code:
z(1)<= d(2) or d(3) or d(6) or d(7); library IEEE;
z(0)<= d(1) or d(3) or d(5) or d(7); use IEEE.STD_LOGIC_1164.ALL;
end dataflow; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Behavioral Modeling: entity or4 is
library IEEE; Port ( a : in std_logic;
use IEEE.STD_LOGIC_1164.ALL; b : in std_logic;
use IEEE.STD_LOGIC_ARITH.ALL; c : in std_logic;
use IEEE.STD_LOGIC_UNSIGNED.ALL; d : in std_logic;
entity encoder_behv is z : out std_logic);
Port ( d : in std_logic_vector(7 downto 0); end or4;
e : in std_logic; architecture dataflow of or4 is
z : out std_logic_vector(2 downto 0)); begin
end encoder_behv; z<=a or b or c or d;
architecture Behavioral of encoder_behv is end dataflow;
begin
p1:process(d,e) DECODERS:
begin LOGIC DIAGRAM:
if (e='1') then
case d is
when "10000000"=>z<="000";
when "01000000"=>z<="001";
when "00100000"=>z<="010";
when "00010000"=>z<="011";
when "00001000"=>z<="100";
when "00000100"=>z<="101";
when "00000010"=>z<="110";
when "00000001"=>z<="111";
when others=>z<="ZZZ";
end case;
else
z<="XXX";
end if;
end process p1;
end Behavioral;

Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_struct is
Port ( d : in std_logic_vector(7 downto 0);
z : out std_logic_vector(2 downto 0));
VHDL SOURCE CODE:
end encoder_struct;
architecture structural of encoder_struct is
Dataflow Modeling:
component or4
library IEEE;
port(a,b,c,d:instd_logic;
use IEEE.STD_LOGIC_1164.ALL;
z:out std_logic);
use IEEE.STD_LOGIC_ARITH.ALL;
end component;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
begin
entity decoder_dataflow is
o1:or4 port map (d(4),d(5),d(6),d(7),z(0));
Port ( a : in std_logic;
o2:or4 port map (d(2),d(3),d(6),d(7),z(1));
b : in std_logic;
o3:or4 port map (d(1),d(3),d(5),d(7),z(2));
e : in std_logic;
end structural;
z : out std_logic_vector(3 downto 0));
end decoder_dataflow;
architecture dataflow of decoder_dataflow is
signal abar,bbar:std_logic;
begin
abar<= not a;
bbar<= not b;
z(0)<= not (abar and bbar and e);
z(1)<= not (abar and b and e);
z(2)<= not (a and bbar and e);
z(3)<= not (a and b and e);
end dataflow;
port(a:instd_logic;
z:out std_logic);
end component;
signal abar,bbar:std_logic;
begin
n1:not1 port map (a,abar);
n2:not1 port map (b,bbar);
a1:nand3 port map (abar,bbar,e,z(0));
a2:nand3 port map (abar,b,e,z(1));
a3:nand3 port map (a,bbar,e,z(2));
a4:nand3 port map (a,b,e,z(3));
end structural;

Behavioral Modeling: nand3 component source code:

library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_behv is entity nand3 is
Port ( a : in std_logic; Port ( a : in std_logic;
b : in std_logic; b : in std_logic;
e : in std_logic; c : in std_logic;
z : out std_logic_vector(3 downto 0)); z : out std_logic);
end decoder_behv; end nand3;
architecture Behavioral of decoder_behv is architecture dataflow of nand3 is
begin begin
p1:process(a,b) z<= not (a and b and c);
begin end dataflow;
if (e='1') then
z(0)<= not a and not b ; not1 component source code:
z(1)<= not a and b; library IEEE;
z(2)<= a and not b; use IEEE.STD_LOGIC_1164.ALL;
z(3)<= a and b; use IEEE.STD_LOGIC_ARITH.ALL;
else use IEEE.STD_LOGIC_UNSIGNED.ALL;
z<="1111"; entity not1 is
end if; Port ( a : in std_logic;
end process p1; z : out std_logic);
end Behavioral; end not1;
architecture dataflow of not1 is
Structural Modeling: begin
library IEEE; z<= not a;
use IEEE.STD_LOGIC_1164.ALL; end dataflow;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; MULTIPLEXER AND DEMULTIPLEXER
entity decoder_struct is AIM
Port ( a : in std_logic; To develop the source code for multiplexer and
b : in std_logic; demultiplexer by using VHDL/VERILOG and obtain the
e : in std_logic; simulation, synthesis, place and route and implement
z : out std_logic_vector(3 downto 0)); into FPGA.
end decoder_struct; ALGORITHM
architecture structural of decoder_struct is Step1: Define the specifications and initialize the design.
component nand3 Step2: Declare the name of the entity and architecture by
port(a,b,c:instd_logic; using VHDL source code.
z:out std_logic); Step3: Write the source code in VERILOG.
end component; Step4: Check the syntax and debug the errors if found,
component not1 obtain the synthesis report.
Step5: Verify the output by simulating the source code. elsif (s(0)<='0' and s(1)<='1') then
Step6: Write all possible combinations of input using the y<=d(1);
test bench. elsif (s(0)<='1' and s(1)<='0') then
Step7: Obtain the place and route report. y<=d(2);
MULTIPLEXER: else
LOGIC DIAGRAM: y<=d(3);
end if;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_struct is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_struct;
VHDL SOURCE CODE: architecture structural of mux_struct is
Dataflow Modeling: component not1
library IEEE; port(a:instd_logic;
use IEEE.STD_LOGIC_1164.ALL; z:out std_logic);
use IEEE.STD_LOGIC_ARITH.ALL; end component;
use IEEE.STD_LOGIC_UNSIGNED.ALL; component and3
entity mux_dataflow is port(a,b,c:instd_logic;
Port ( d : in std_logic_vector(3 downto 0); z:out std_logic);
s : in std_logic_vector(1 downto 0); end component;
y : out std_logic); component or4
end mux_dataflow; port(a,b,c,d:instd_logic;
architecture dataflow of mux_dataflow is z:out std_logic);
signal s0bar,s1bar,p,q,r,st:std_logic; end component;
begin signal s0bar,s1bar,p,q,r,st:std_logic;
p<= d(0) and s0bar and s1bar; begin
q<= d(1) and s0bar and s(1); n1:not1 port map (s(0),s0bar);
r<= d(2) and s(0) and s1bar; n2:not1 port map (s(1),s1bar);
st<= d(3) and s(0) and s(1); a1:and3 port map (d(0),s0bar,s1bar,p);
s0bar<= not s(0); a2:and3 port map (d(1),s0bar,s(1),q);
s1bar<= not s(1); a3:and3 port map (d(2),s(0),s1bar,r);
y<= p or q or r or st; a4:and3 port map (d(3),s(0),s(1),st);
end dataflow; o1:or4 port map (p,q,r,st,y);
Behavioral Modeling: end structural;
library IEEE; and3 component source code:
use IEEE.STD_LOGIC_1164.ALL; library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
entity mux_behv is use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( d : in std_logic_vector(3 downto 0); entity and3 is
s : in std_logic_vector(1 downto 0); Port ( a : in std_logic;
y : out std_logic); b : in std_logic;
end mux_behv; c : in std_logic;
architecture Behavioral of mux_behv is z : out std_logic);
begin end and3;
p1:process(d,s) architecture dataflow of and3 is
begin begin
if (s(0)<='0' and s(1)<='0') then z<=a and b and c;
y<=d(0); end dataflow;
not1 component source code: s : in std_logic_vector(1 downto 0);
library IEEE; z : out std_logic_vector(3 downto 0));
use IEEE.STD_LOGIC_1164.ALL; end demux_dataflow;
use IEEE.STD_LOGIC_ARITH.ALL; architecture dataflow of demux_dataflow is
use IEEE.STD_LOGIC_UNSIGNED.ALL; signal s0bar,s1bar:std_logic;
entity not1 is begin
Port ( a : in std_logic; s0bar<= not s(0);
z : out std_logic); s1bar<= not s(1);
end not1; z(0)<=d and s0bar and s1bar;
architecture dataflow of not1 is z(1)<=d and s0bar and s(1);
begin z(2)<=d and s(0) and s1bar;
z<= not a; z(3)<=d and s(0) and s(1);
end dataflow; end dataflow;
Behavioral Modeling:
or4 component source code: library IEEE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_behv is
entity or4 is Port ( d : in std_logic;
Port ( a : in std_logic; s : in std_logic_vector(1 downto 0);
b : in std_logic; z : out std_logic_vector(3 downto 0));
c : in std_logic; end demux_behv;
d : in std_logic; architecture Behavioral of demux_behv is
z : out std_logic); begin
end or4; p1:process(d,s)
architecture dataflow of or4 is begin
begin if (s(0)<='0' and s(1)<='0') then
z<=a or b or c or d; z(0)<=d;
end dataflow; z(1)<='Z';
DEMULTIPLEXER: z(2)<='Z';
LOGIC DIAGRAM: z(3)<='Z';
elsif (s(0)<='0' and s(1)<='1') then
z(0)<='Z';
z(1)<=d;
z(2)<='Z';
z(3)<='Z';
elsif (s(0)<='1' and s(1)<='0') then
z(0)<='Z';
z(1)<='Z';
z(2)<=d;
z(3)<='Z';
else
z(0)<='Z';
z(1)<='Z';
z(2)<='Z';
z(3)<=d;
end if;
end process p1;
end Behavioral;
Dataflow Modeling: Structural Modeling:
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_dataflow is entity demux_struct is
Port ( d : in std_logic; Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0); To develop the source code for flip flops by using
z : out std_logic_vector(3 downto 0)); VHDL/VERILOG and Obtained the simulation,
end demux_struct; synthesis,
architecture structural of demux_struct is place and route and implement into FPGA.
component not1 ALGORITHM:
port(a:instd_logic; Step1: Define the specifications and initialize the design.
z:out std_logic); Step2: Declare the name of the entity and architecture by
end component; using VHDL source code.
component and3 Step3: Write the source code in VERILOG.
port(a,b,c:instd_logic; Step4: Check the syntax and debug the errors if found,
z:out std_logic); obtain the synthesis report.
end component; Step5: Verify the output by simulating the source code.
signal s0bar,s1bar:std_logic; Step6: Write all possible combinations of input using the
begin test bench.
n1:not1 port map (s(0),s0bar); Step7: Obtain the place and route report.
n2:not1 port map (s(1),s1bar); SR FLIPFLOP:
a1:and3 port map (d,s0bar,s1bar,z(0)); LOGIC DIAGRAM:
a2:and3 port map (d,s0bar,s(1),z(1));
a3:and3 port map (d,s(0),s1bar,z(2));
a4:and3 port map (d,s(0),s(1),z(3));
end structural;
and3 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and3 is TRUTH TABLE:
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end and3;
architecture dataflow of and3 is
begin
z<=a and b and c;
end dataflow;
not1 component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; VHDL SOURCE CODE:
use IEEE.STD_LOGIC_UNSIGNED.ALL; Behavioral Modeling:
entity not1 is library IEEE;
Port ( a : in std_logic; use IEEE.STD_LOGIC_1164.ALL;
z : out std_logic); use IEEE.STD_LOGIC_ARITH.ALL;
end not1; use IEEE.STD_LOGIC_UNSIGNED.ALL;
architecture dataflow of not1 is entity srff is
begin Port ( s : in std_logic;
z<= not a; r : in std_logic;
end dataflow; clk : in std_logic;
rst : in std_logic;
q : inoutstd_logic;
qbar : inoutstd_logic);
end srff;
architecture Behavioral of srff is
begin
FLIP FLOPS process(s,r,clk,rst,q,qbar)
AIM: begin
if (rst='1') then clk : in std_logic;
q<='0'; rst : in std_logic;
qbar<='1'; q : inoutstd_logic;
elsif (clk='1' and clk'event) then qbar : inoutstd_logic);
if (s='0' and r='0') then end jkff;
q<=q; architecture Behavioral of jkff is
qbar<=qbar; begin
elsif (s='0' and r='1') then process(j,k,clk,rst,q,qbar)
q<='0'; begin
qbar<='1'; if (rst='1') then
elsif (s='1' and r='0') then q<='0';
q<='1'; qbar<='1';
qbar<='0'; elsif (clk='1' and clk'event) then
else if (j='0' and k='0') then
q<='X'; q<=q;
qbar<='X'; qbar<=qbar;
end if; elsif (j='0' and k='1') then
end if; q<='0';
end process; qbar<='1';
end Behavioral; elsif (j='1' and k='0') then
q<='1';
JK FLIPFLOP: qbar<='0';
LOGIC DIAGRAM: else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;

D FLIPFLOP:
LOGIC DIAGRAM:

TRUTH TABLE:

TRUTH TABLE:

VHDL SOURCE CODE:

Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in std_logic;
k : in std_logic;
VHDL SOURCE CODE:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d : in std_logic;
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
q : inoutstd_logic; q : inoutstd_logic;
qbar : inoutstd_logic); qbar : inoutstd_logic);
end dff; end tff;
architecture Behavioral of dff is architecture Behavioral of tff is
begin begin
process(d,clk,rst,q,qbar) process(t,clk,rst,q,qbar)
begin begin
if (rst='1') then if (rst='1') then
q<='0'; q<='0';
qbar<='1'; qbar<='1';
elsif (clk='1' and clk'event) then elsif (clk='1' and clk'event) then
if (d='0') then if (t='0') then
q<='0'; q<=q;
qbar<='1'; qbar<=qbar;
else else
q<='1'; q<=not q;
qbar<='0'; qbar<=not qbar;
end if; end if;
end if; end if;
end process; end process;
end Behavioral; end Behavioral;

T FLIPFLOP:
LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOURCE CODE:

Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
SHIFT REGISTERS
AIM:
To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation, synthesis,
place and route and implement into FPGA.
ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

SERIAL-IN SERIAL-OUT SHIFT REGISTER:

LOGIC DIAGRAM:

VHDL SOURCE CODE: x(2)<=x(1);

Behavioral Modeling: x(3)<=x(2);
library IEEE; x(4)<=x(3);
use IEEE.STD_LOGIC_1164.ALL; x(5)<=x(4);
use IEEE.STD_LOGIC_ARITH.ALL; x(6)<=x(5);
use IEEE.STD_LOGIC_UNSIGNED.ALL; x(7)<=x(6);
entity siso is q<=x(7);
Port ( d : in std_logic; end if;
clk : in std_logic; end process;
rst : in std_logic; end Behavioral;
q : out std_logic);
end siso;
architecture Behavioral of siso is
signal x:std_logic_vector(7 downto 0);
begin
process(d,clk,rst)
begin
if (rst='1') then
q<='X';
elsif (clk='1' and clk'event) then
x(0)<=d;
x(1)<=x(0);
SERIAL IN PARALLEL OUT SHIFT REGISTER:
LOGIC DIAGRAM :
VHDL SOURCE CODE:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inoutstd_logic_vector(7 downto 0));
end sipo;
architecture Behavioral of sipo is
begin
process(d,clk,rst)
begin
if (rst='1') then
q<="ZZZZZZZZ";
elsif (clk='1' and clk'event) then
q(0)<=d;
q(1)<=q(0);
q(2)<=q(1);
q(3)<=q(2);
q(4)<=q(3);
q(5)<=q(4);
q(6)<=q(5);
q(7)<=q(6);
end if;
end process;
end Behavioral;

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:

LOGIC DIAGRAM :
VHDL SOURCE CODE:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pipo is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(7 downto 0));
end pipo;
architecture Behavioral of pipo is
begin
process(d,clk,rst)
begin
if (rst='1') then
q<="ZZZZZZZZ";
elsif (clk='1' and clk'event) then
q(0)<=d(0);
q(1)<=d(1);
q(2)<=d(2);
q(3)<=d(3);
q(4)<=d(4);
q(5)<=d(5);
q(6)<=d(6);
q(7)<=d(7);
end if;
end process;
end Behavioral;

PARALLEL-IN SERIAL-OUT SHIFT REGISTER:

LOGIC DIAGRAM :
VHDL SOURCE CODE: if (rst='1') then
Behavioral Modeling: q<='Z';
library IEEE; else
use IEEE.STD_LOGIC_1164.ALL; if (load='0') then
use IEEE.STD_LOGIC_ARITH.ALL; x:=d;
use IEEE.STD_LOGIC_UNSIGNED.ALL; else
entity piso is q<=x(0);
Port ( d : in std_logic_vector(7 downto 0); x(0):=x(1);
clk : in std_logic; x(1):=x(2);
rst : in std_logic; x(2):=x(3);
load : in std_logic; x(3):=x(4);
q : out std_logic); x(4):=x(5);
end piso; x(5):=x(6);
architecture Behavioral of piso is x(6):=x(7);
begin x(7):='Z';
process(d,clk,rst,load) end if;
variable x:std_logic_vector(7 downto 0); end if;
begin end if;
if (clk='1' and clk'event) then end process;
end Behavioral;

SYNCHRONOUS AND ASYNCHRONOUS COUNTER

AIM:
To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.
ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

SYNCHRONOUS COUNTER:
LOGIC DIAGRAM:
VHDL SOURCE CODE: t2:tff port map (q(0),clk,rst,q(1),x4);
Structural Modeling: t3:tff port map (x1,clk,rst,q(2),x5);
library IEEE; t4:tff port map (x2,clk,rst,q(3),x6);
use IEEE.STD_LOGIC_1164.ALL; a1:and2 port map (q(0),q(1),x1);
use IEEE.STD_LOGIC_ARITH.ALL; a2:and2 port map (x1,q(2),x2);
use IEEE.STD_LOGIC_UNSIGNED.ALL; end structural;
entity syncounter is
Port ( clk : in std_logic; tff component source code:
rst : in std_logic; library IEEE;
q : inoutstd_logic_vector(3 downto 0)); use IEEE.STD_LOGIC_1164.ALL;
end syncounter; use IEEE.STD_LOGIC_ARITH.ALL;
architecture structural of syncounter is use IEEE.STD_LOGIC_UNSIGNED.ALL;
component tff entity tff is
port(t,clk,rst:instd_logic; Port ( t : in std_logic;
q,qbar:inoutstd_logic); clk : in std_logic;
end component; rst : in std_logic;
component and2 q : inoutstd_logic;
port(a,b:instd_logic; qbar : inoutstd_logic);
z:out std_logic); end tff;
end component; architecture Behavioral of tff is
signal x1,x2:std_logic; begin
signal x3,x4,x5,x6:std_logic:='Z'; process(t,clk,rst,q,qbar)
begin begin
t1:tff port map ('1',clk,rst,q(0),x3); if (rst='1') then
q<='0';
qbar<='1'; end Behavioral;
elsif (clk='1' and clk'event) then
if (t='0') then and2 component source code:
q<=q; library IEEE;
qbar<=qbar; use IEEE.STD_LOGIC_1164.ALL;
else use IEEE.STD_LOGIC_ARITH.ALL;
q<=not q; use IEEE.STD_LOGIC_UNSIGNED.ALL;
qbar<=not qbar; entity and2 is
end if; Port ( a : in std_logic;
end if; b : in std_logic;
end process; z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<=a and b;
end dataflow;

ASYNCHRONOUS COUNTER:
LOGIC DIAGRAM:

VHDL SOURCE CODE:

Structural Modeling:
library IEEE; qbar : inoutstd_logic);
use IEEE.STD_LOGIC_1164.ALL; end tff;
use IEEE.STD_LOGIC_ARITH.ALL; architecture Behavioral of tff is
use IEEE.STD_LOGIC_UNSIGNED.ALL; begin
entity asyncounter is process(t,clk,rst,q,qbar)
Port ( clk : in std_logic; begin
rst : in std_logic; if (rst='1') then
q : inoutstd_logic_vector(3 downto 0)); q<='0';
end asyncounter; qbar<='1';
architecture structural of asyncounter is elsif (clk='1' and clk'event) then
component tff if (t='0') then
port(t,clk,rst:instd_logic; q<=q;
q,qbar:inoutstd_logic); qbar<=qbar;
end component; else
signal x1,x2,x3:std_logic; q<=not q;
signal x4:std_logic:='Z'; qbar<=not qbar;
begin end if;
t1:tff port map ('1',clk,rst,q(0),x1); end if;
t2:tff port map ('1',x1,rst,q(1),x2); end process;
t3:tff port map ('1',x2,rst,q(2),x3); end Behavioral;
t4:tff port map ('1',x3,rst,q(3),x4);
end structural;
tff component source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inoutstd_logic;