TC1

Termen limita: 10 marite 2010, 8pm

Problemele 1.1 si 1.2 (vezi pag. 19 din text book).

Problem 1.1 Let be the full 4-bit adder described in the following Verilog module:

module fullAdder( output [3:0] out ,

output crOut , // carry output
input [3:0] in0 ,
input [3:0] in1 ,
input crIn ); // carry input

wire [4:0] sum ;

assign sum = in0 + in1 + crIn ;

assign out = sum[3:0] ;
assign crOut = sum[4] ;

endmodule

Use the module fullAdder to design the following 16-bit full adder:

module bigAdder( output [15:0] out ,

output crOut , // carry output
input [15:0] in0 ,
input [15:0] in1 ,
input crIn ); // carry input
// ???

endmodule

The resulting project will be simulated designing the appropriate test module.
Problema 1.1

Adder.v

module fullAdder( output [3:0] out , // sum output

output crOut , // carry output
input [3:0] in0 ,
input [3:0] in1 ,
input crIn ); // carry input

wire [4:0] sum ;

assign sum = in0 + in1 + crIn ;

assign out = sum[3:0] ;
assign crOut = sum[4] ;

endmodule

module bigAdder( output [15:0] out , // adder output

output crOut , // carry_out output
input [15:0] in0 ,
input [15:0] in1 ,
input crIn ); // carry_in input

wire carry ;

wire c1 ;
wire c2 ;
wire c3 ;

wire [3:0] out3,out2,out1,out0;

fullAdder f0 (
.in0(in0[3:0]) ,
.in1(in1[3:0]) ,
.crIn(crIn) ,
.out(out0) ,
.crOut (c1)
);

fullAdder f1 (
.in0(in0[7:4]) ,
.in1(in1[7:4]) ,
.crIn(c1) ,
.out(out1) ,
.crOut(c2)
);

fullAdder f2 (
.in0(in0[11:8]) ,
.in1(in1[11:8]) ,
.crIn (c2) ,
.out(out2) ,
.crOut(c3));
fullAdder f3 (
.in0(in0[15:12]) ,
.in1(in1[15:12]) ,
.crIn (c3) ,
.out(out3) ,
.crOut(carry)
);

assign out = {out3,out2,out1,out0};

endmodule

Adder_test.v

module Adder_test ;
reg [15:0] in0, in1;
reg crIn;
wire [15:0] out;
wire crOut;

initial
begin in0=0;
in1=0;
crIn=0;
#1 in0=16'b0000_0000_0000_0001;
#1 in1=16'b0100_0101_0000_1011;
#1 crIn=1'b0;
#1 in0=16'b1111_0010_1101_1101;
#1 crIn=1'b1;
#1 in1=16'b1101_1001_1111_1111;
end

bigAdder dut ( .out(out),

.crOut(crOut),
.in0(in0),
.in1(in1),
.crIn(crIn)
);
endmodule
Simulare in Modelsim
Problem 1.2 Draw the block schematic of the following design:

module topModule( output [7:0] out,

input [7:0] in1,
input [7:0] in2,
input [7:0] in3);
wire [7:0] wire1, wire2;

bottomModule mod1( .out(wire1 ),

.in1(in1 ),
.in2(in2 )),
mod2( .out(wire2 ),
.in1(wire1 ),
.in2(in3 )),
mod3( .out(out ),
.in1(in3 ),
.in2(wire2 ));
endmodule

module bottomModule( output [7:0] out,

input [7:0] in1,
input [7:0] in2);
// ...
endmodule
Synthesize it to test your solution.

Rezolvare:

Sistemul are 3 intrari : in1,in2 si in3 pe 8 biti si o iesire out pe 8 biti, iar modulele secundare
(mod1,mod2 si mod3) preiau ca date de intrare fie intrarile sistemului , fie intrarile transmise
prin variabilele wire1 si wire2 (care reprezinta iesire ale modulelor mod1 si mod2) sau ca in
cazul modului mod3 care preia date de pe intrarea in3 a sistemului si de pe intrarea
transmisa prin variabila wire2.
Modulele mod1,mod2 si mod3 sunt instantiate in modulul topModule.
O schema posibila pentru implementare sistemului ar fi urmatoarea: