GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

Discussion and CMOS Design of Logic Latches

Muhammad Fahd Waseem, Member, IEEE

AbstractThis assignment answers questions about the design and physical CMOS layout of electronic logic latches. It clearly indicates their operation using block diagrams and related functions, and demonstrates functionality in gate & transistor schematics and physical level layouts. Note that ip-ops are expressly removed from this paper, as they are non-transparent, while latches are transparent. Index TermsLatches, Flip-Flops, ASIC, VLSI, MicroWind, Switch Level, Physical Level

Fig. 1: (a) SR Latch, and (b) D Latch

I. I NTRODUCTION N electronics, a latch is a kind of bistable multivibrator, an electronic circuit that has two stable states and therefore can store one bit of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as ip-ops. While gates have to be built directly from transistors, latches can be built from gates, and ip-ops can be built from latches. Both latches and ip-ops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a ipop is that a latch does not have a clock signal, whereas a ip-op always does [1]. Generally dened, a clock is an edge triggering mechanism, while an enable (or a gate) is a level triggering mechanism. In other words, a true latch is always asynchronous while a ip-op is always synchronous. Because the distinction between a ip-op and a latch is clear, this paper will adhere to the correct technical denitions as per the title, and describe proper latches only. Latches may be gated, or non-gated, depending on whether they have an enable input.

Fig. 2: Blocks for (a) SR Latch, and (b) D Latch

is held low, then the Q output is forced low, and stays low when R returns to low. See Table I. The NOR gates in the SR latch can also be replaced by NAND gates, to gain an SR latch i.e. an SR latch with active low inputs. B. Sub latch types based on the SR Latch The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in highfrequency digital circuits. Although this condition is usually avoided, it can be useful in some applications. To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-restricted combinations. That can be: Q = 1 (1,0) referred to as an S-latch Q = 0 (0,1) referred to as an R-latch Keep state (0,0) referred to as an E-latch Toggle the output referred to as a JK-latch TABLE I: State Table for SR Latch
S 0 0 1 1 R 0 1 0 1 Output Keep State Q=0 Q=1 Restricted Combination

II. L ATCH T YPES A. SR Latches When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of crosscoupled logic gates. The stored bit is present on the output marked Q. See Fig. 1 & 2. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S
This is NOT a research paper, though every attempt has been made to keep the information in this document as accurate as possible. This paper is released under the Creative Commons Share-Alike license only. A This paper has been typeset in L TEX 2 , using the standard IEEEtran class in two-sided, Journal paper mode and A4 page sizing.

GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

TABLE II: State Table for D Latch

D 1 0 Output Q=1 Q=0

E. Gated D Latches The gated D latch works in the same way as the D latch with the SR latch. The two non-gate inputs to the gated SR latch are bound by a NOT gate. With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high. See Fig. 3 & 4 and Table III. There are no invalid states. III. S PECIFICATIONS We are required to design optimized D latches as dened by the project guidelines for the CS465 Asic Design course project [2]. These requirements are drawn from the course textbook (Introduction to VLSI Circuits and Systems, by John P. Uyemura). Standard design rules and methodologies must be applied to design the stated latches. Verilog must be used as the HDL, block diagrams must be displayed and simulations must all be complete. IV. D ESIGN M ETHODOLOGY It is our requirement to design for, and test, the given objectives, but not produce fabricatable packages. So our design methodology shall follow the standard CMOS-VLSI design ow for digital circuits, 1) System Specication: What is the application / system we need to design, and with what parameters. 2) System Design and Verication: To be done on a high level schematic simulator, Verilog HDL (behavioral), or an equivalent high level model extractor. For less complicated specications, this step may be skipped. 3) Logic Synthesis: Reducing the system design to gate level descriptions, and subsequent verication. This usually entails a simulation or test in Verilog at the gate / RTL level, or a dedicated logic level simulator. 4) Circuit Design: For CMOS design, this entails reducing the gate level design into an optimized transistor level circuit, and subsequent testing. 5) Physical Design: The circuit design is converted into optimized silicon layouts. Layouts at this level are generally optimized according to a set of design rules, and tested using extended SPICE models. V. D ESIGN E NVIRONMENT The design environment is dened as the ecosystem of software tools and kits available during the design phase of the project [3]. A. Software Tools

Fig. 3: Gated, (a) SR Latch, and (b) D Latch

C. D Latches This latch exploits the fact that in the two active input combinations (01 and 10) of the SR latch, R is the complement of S. The NOT gate converts the two D input states (0 and 1) to these two input combinations for the SR latch. Thus a D-latch may be considered as a one-input asynchronous SR latch. This conguration prevents from applying the restricted combination to the inputs. It is also known as transparent latch, or data latch. The word transparent comes from the fact that the signal propagates directly through the circuit, from the input D to the output Q. See Fig. 1 & 2 and Table II. Transparent latches are typically used as I/O ports or in asynchronous systems. They are available as integrated circuits, usually with multiple latches per circuit. D. Gated SR Latch A gated SR latch can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable). See Fig. 3 & 4. With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent. With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high. See Table III.

Fig. 4: Blocks for Gated (a) SR Latch, and (b) D Latch

TABLE III: State Table for Gated SR and D Latches

E/C 0 1 State No Change / Keep State Same as Regular Latch

GNU CC: The GNU C Compiler. Used in a Linux environment for testing SystemC code. ModelSim: The industry standard HDL & system level synthesis and simulation suite. DSCH: A digital schematic editor and simulator, written for academic purposes by Dr. Etienne Sicard, based in Toulouse, France [4]. Wind (MicroWind): A physical layout design tool and simulator for CMOS circuits, also written by Dr. Etienne Sicard.

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES

B. BSIM4: Berkeley MOSFET SPICE Simulator MicroWind integrates BSIM4 (Berkeley MOSFET SPICE Simulator) into the simulations it performs. BSIM4, as an extension of BSIM model, addresses the MOSFET physical effects into sub-100nm regime. It is a physics-based, accurate, scalable, robustic and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. BSIM is charted by the Compact Model Council (CMC) [5]. It is a consortium of semiconductor companies and simulator vendors world-wide promoting BSIM3v3 development as the industry standard compact model. The council is afliated with Electronic Industries Alliance (EIA). BSIM4 is handled from within the MicroWind interface using a series of parameters. As such, it is among the most accurate SPICE simulators for CMOS available in the market. While commercial EDA tool vendors have models further advanced in accuracy, BSIM4 is perfectly sufcient for our requirements. C. Restrictions of the Used Software Tools Our selection of software tools imposes some restrictions of the kind of design that can be implemented. ModelSim is the least restricting of those, because of its pervasive commercial background. Its standard method for HDL simulations is a slightly old technique, whereby the testbench must be created from HDL itself. DSCH and MicroWind suffer from a limit on the size of the netlist. Extremely large circuits cannot be simulated on them. The macros for collective operations are poor: undo is limited to one operation, collective resizing does not follow polygon rules, attributes cannot be changed by multiple selection, and so on. Moreover, DSCH tends to xate the orientation of the symbols for transistors, making the re-orienting of these particularly painstaking. MicroWind also does not support cell methods. This may be a major problem when designing large circuits that rely on multiple repeating units. Despite these restrictions, the design environment is sufcient for our requirements. Our specications do not call for large complex designs, but highly optimized small designs. We do not require the use of cells in our design, and by issuing software commands carefully (and taking repeated backups), we can avoid the pitfalls of the lack of GUI macros in DSCH and MicroWind. VI. H IGH L EVEL B EHAVIORAL M ODELING IN S YSTEM C SystemC is a language built in C++ that spans from concept to implementation in hardware and software. The IEEE Standards Association approved the standard for the SystemC library as IEEE Std. 1666 2005 [6]. We used SystemC to design a basic D latch, just to test the highest level of abstraction available. The advantage of using SystemC lay in the true high-level abstraction it offers,

as opposed to the pseudo behavioral abstraction offered by Verilog in the always blocks it uses. Appendix A shows the code we used to implement the latch. The text results immediately follow it. It may be noted that the testing was extremely rudimentary, and not very exhaustive in either scope or optimization. The purpose was just to get a taste of the language. In our case, the Mint 6 distribution of Linux was used for the compilation. VII. N OTES ON THE L AYOUTS I MPLEMENTED Throughout our layout designs, it should be noted that we implemented our design rules based on the CMOS 90nm, 6 Metal Copper, Strained SiGe LowK fabrication process. For this process, some of the design rules pertinent to our requirements are given in Appendix B. It may be noted that the design rules le species many other rules, and many specications for use by the SPICE engine in MicroWind, but to specify them here is beyond the scope of this paper. We used design rules, with 1 = 0.050m. 2 is the smallest possible channel length, according to the design rules. Electrical symmetry was maintained wherever possible. We decided to use a baseline NFET size, and then resize the PFETs accordingly to achieve the symmetry. The aspect ratio of the baseline NFET was chosen to be 5, i.e. 10/2 due to the channel length sizing restriction. The channel length is always kept at = 2, for both PFETs and NFETs. In resizing, only the channel width was changed for the PFETs. The mobility ratio r (of P-channel FETs to N-channel FETs) depends on the manufacturing process. However, it is rare that exact mobilities are provided. In that case, it is possible to use the IDS to VDS curves of tranistors to nd r because mobility () (current carried). So, r= IDS, N N = P IDS, P

All other variables constant

To process the given equation, we generated IV curves for one NFET and one PFET, with channel dimensions for both being sized at 10 2. The curves are shown in Fig. 5. Choosing the values for VDS = VGS = 1.20V, we nd, r= IDS, N 650A = 1.86 1.86 = 2 IDS, P 350A

Thus, we shall use the value of r = 2 where needed. The unusual shapes and sizes of interlayer contacts will be noted: these are to optimize contact resistances while complying with the design rules. These lead to higher signal delity. The physical layouts were almost entirely made in levels Metal 1 and below. Only in the case of a capacitance requirement were we forced to move to Metal 2. N-wells were all rooted to the highest potential, and the substrate was grounded to the lowest potential in all cases. Circuit setup times in the SPICE / BSIM4 / MicroWind simulations were ignored - these are typically within the rst 200ps. For logic values, VDD was considered 1.20V and VSS 0.00V. The colour and sketchmark legend given in Fig. 6 is followed throughout this paper for physical CMOS layouts.

GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

Fig. 5: IV Curves for Similarly Sized NFETs and PFETs, for increasing biasing

Fig. 6: Physical CMOS Layout Legend Fig. 7: Transistor Level Schematic of Basic D Latch VIII. BASIC D L ATCH The basic D latch logic on a transistor level was implemented in DSCH. Fig. 7 shows the created schematic. This was also simulated in Verilog, shown in Fig. 8. The code for the simulation can be found in Appendix C. It can be seen that the output Q immediately follows D. This was then converted to a CMOS layout, as shown in Fig. 9. For creating electrical signal symmetry, PFETs were increased in size. Note the inconsistent sizing of the PFETs (the PFETs for the main circuit are larger than the PFET for the inverter). This is because the 2 PFETs are connected in series the P half of the circuit for any given signal route, which

means the signal propagates half as fast. Using the mobility constant ratio of 2, the PFETs thus needed to be 4 times as large as the NFET (which were baseline-sized) for electrical symmetry. The simulation results are shown in Fig. 10. The MicroWind default simulation parameters for BSIM4 were used. As can be seen, the output Q immediately takes the logic of the input, showing the overall success of the design.

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES

Fig. 8: Verilog Simulation for Basic D Latch at Transistor Level

Fig. 11: D Latch w/Enable Logic Schematic

Fig. 9: CMOS Layout of Basic D Latch

Fig. 13: D Latch w/Enable Transistor AOI Schematic

A. D Latch at Transistor Level The D latch (with enable) at transistor level is an AOI (AndOr-Invert) conversion of the logic schematic shown in Fig. 11. The transistor level schematic is shown in Fig. 13. The Verilog code for this schematic is given in Appendix E, while the simulation is shown in Fig. 14. B. D Latch with Enable, Physical Layout Converting the transistor level schematic into a physical layout, while maintaining optimum circuit characteristics, turned out to be a bit of a challenge. Fig. 15 shows the converted layout. Note how the metal lines arc around the polylines to avoid the involvement of an extra metal layer for interconnection. By optimizing the placement of the ngers in the PFETs and NFETs and intelligent connection in parallel and series, the size of the circuit was kept to a minimum while also keeping signal delays at a minimum. Electrical symmetry too, was maintained. Fig. 16 shows the SPICE simulation results from MicroWind. The circuit characteristics are optimal: Q follows

Fig. 10: SPICE Simulation of Basic D Latch Layout

IX. D L ATCH WITH E NABLE C ONTROL The schematic created in DSCH (Fig. 11) at gate level is identical to the D latch shown in Fig. 3. The Verilog code for this can be found in Appendix D, and the simulation is shown in Fig. 12. Q follows D only when En is high. Else, the AND gates are disabled and D does not ow through the latch.

GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

Fig. 12: Verilog Simulation for D Latch w/Enable Gate Logic

Fig. 14: D Latch w/Enable Transistor Verilog Simulation

Fig. 16: D Latch w/Enable Physical Layout Simulation

A. Basic Bistable D Latch The Verilog code for a basic bistable D latch is given in Appendix F, and the simulation is shown in Fig. 17. The transistor level schematic is shown Fig. 18. One important thing to note is that bistables need to be forced to change state by a strong voltage source. The stable output needs a current inux to change polarity, so a high impedance signal will not change the output. A low impedance voltage source / signal is thus necessary. This is the reason bistables are slower than the AOI latches. Converting this to physical layout was easy as it was simply connection of two CMOS inverters in feedback loop. The layout is shown in Fig. 19 and the SPICE simulation result in Fig. 20. As can be seen, Q follows D, thus the implementation is successful. B. Bistable D Latch with Controlled Loading One way to make the bistable latch faster and perform without the current inuxes is to add to gating switches. Transmission gates are often used for this, but using simply

Fig. 15: D Latch w/Enable Physical Layout

D as long as Enabled. Else, it keeps the value it had before being unEnabled. X. B ISTABLE C IRCUITS AS L ATCHES Bistables are circuits with two stable states. Bistable circuits can be also be used as latches. The advantage of using bistables as latches is that their sizes are reduced, but the disadvantage is that they are slow and can have glitches during input changes due to the feedback mechanism they rely on.

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES

Fig. 17: Basic D Latch Bistable Verilog Simulation

Fig. 18: Basic D Latch Bistable Transistor Level Schematic NFETs if usually better, to avoid routing difculties and to prevent the circuit from gaining undue size (which was the advantage of the bistables). Appendix G shows the Verilog code for such a conguration, and Fig. 21 shows the simulation results from the Verilog. Fig. 22 shows a transistor level schematic. When the control, C, is high, the feedback loop is broken and the input gate from D is opened. This allows the value of D to be taken up by the circuit. When C goes low, the feedback loop is reestablished and the input from D is turned off. The simulation shows exactly such a thing happening. XI. C2 MOS L ATCHES This is category of latches that are slightly mis-named, because though C2 MOS stands for Clocked CMOS, they are not edge triggered devices, but level triggered (i.e. gated). Their symmetricity in latch construction makes them compact and highly useful in VLSI applications. A. C2 MOS Static D Latch These are so called because they use a feedback mechanism, not much unlike the bistable with load control, to hold a value of Q as long as necessary. Appendix H shows the Verilog code for such a conguration, and Fig. 23 shows the simulation results from the

Fig. 19: Basic D Latch Bistable Physical Layout

Fig. 20: Basic D Latch Bistable Physical Layout SPICE Simulation

GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

Fig. 21: D Latch Bistable with Loading Control, Verilog Simulation

Fig. 22: D Latch Bistable with Loading Control, Transistor Level Schematic Fig. 24: C2 MOS Static D Latch Transistor Level Schematic

Verilog. ModelSim Verilog had problems simulating the circuit because the feedback loop in this particular latch had more than one element to accept feedback from. Thus, we had to add transistor. These allow Verilog to consider discretized feedback during a time-based simulation and effectively simulate the circuit. Fig. 24 shows a transistor level schematic. Fig. 25 shows the converted physical layout in CMOS, and nally, Fig. 26 shows the SPICE simulation results. The Verilog results, then the SPICE results conrm that when the clk is low, the logic of D ows through and is latched. When clk is high, the rst level of transistors is shut off, and the second layer of transistors hold the value in feedback mode. B. C2 MOS Dynamic D Latch Fig. 27 shows the schematic for a dynamic D latch. They are called dynamic because of the presence of the capacitance as a holding mechanism for the current value of Q. There is no feedback. If the input from the rst level of gates is turned off, the capacitor which was charged, or empty, depending upong D holds the required voltage. But as the FET inputs are not perfect insulators, and there is current leakage otherwise as well, the voltage level at the capacitor changes till it no longer reliably holds the value of Q. The value of D needs to be fed in at repeated intervals or refreshed, thus the word

Fig. 25: C2 MOS Static D Latch Physical Layout

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES

Fig. 23: C2 MOS Static D Latch Verilog Simulation

Fig. 26: C2 MOS Static D Latch Layout SPICE Simulation Fig. 27: C2 MOS Dynamic D Latch Transistor Level Schematic dynamic. Often, the capacitor is not expressly made but relies on the relatively low parasitic capacitance, making the repeated refreshing even more necessary. Due to the compactness of the circuit, however, such latches were used extensively in RAM for computers until better NAND type cells or static RAMs replaced them. We wrote out the required Verilog for the circuit (Appendix I), but were unable to simulate it. The reason turned out to be that only a special kind of Verilog called VerilogAMS can simulate the capacitance necessary for such a simulation. The physical layout, on the other hand (Fig. 28) was easily simulated by the BSIM4 engine in MicroWind, as can be seen in Fig. 29. Note the presence of the large metal layers: these act as capacitor pads to complement the parasitic capacitance, hence improving the characteristics of the circuit. The dimensions of the pads are, 3.85m 4.55m = 17.52(m)2 Using the surface capacitance parameters of the process specications, CS,Metal1 = 28aF/(m)2 CS,Metal2 = 25aF/(m)2 We get the available capacitance as, CAvailable = (28aF/(m)2 + 25aF/(m)2 ) 17.52(m) 930aF
2

Fig. 29: C2 MOS Dynamic D Latch Layout SPICE Simulation

Thus, about 930aF of extra capacitance is available in addition to the parasitic capacitance. It can be seen that the voltage tends to veer away from the previously held value towards an AC average of 0.60V as time passes. But as the value of Q is refreshed, the capacitor once again holds the value anew. XII. C ONCLUSION CMOS latches were designed in a variety of ways, always following the standard VLSI top-down design methodology. The different designs had tradeoffs between performance, size, and glitch states. For gated designs, the smallest design in

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Fig. 28: C2 MOS Dynamic D Latch Physical Layout

terms of area was the bistable with controlled loading. The fastest design with best signal transferrance characteristics was the AOI latch. The C2 MOS latch characteristics were in the middle. A PPENDIX A S YSTEM C C ODE FOR A BASIC D L ATCH
#include "systemc.h" SC_MODULE(d_ff) { sc_in<bool> din; sc_out<bool> dout; void doit() { dout = din; }; SC_CTOR(d_ff) { SC_METHOD(doit); sensitive << din; } }; SC_MODULE_EXPORT(d_ff);

*Executing new @5 ns :: Setting din -> dout SET 0 @10 ns :: Unsetting din -> dout UNSET 1 @15 ns :: Setting din -> dout SET 2 @20 ns :: Unsetting din -> dout UNSET 3 *Terminating simulation

A PPENDIX B D ESIGN RULES FOR THE CMOS 90 NM , 6 M ETAL C OPPER S TRAINED S I G E L OW K P ROCESS
NAME CMOS 90nm, 6 Metal Copper - strained SiGe - LowK * lambda = 0.05 // Lambda is set to half the gate size metalLayers = 6 // Number of metal layers lowK = 3.1 // inter-metal oxide salicide = 1 // salicide option edram = 1 // embedded DRAM process efram = 1 // embedded FRAM process mimcapa = 1 // enable mim capa strain = 1 // Strain material * * Design rules associated to each layer * * Well r101 = 10 (well width) r102 = 11 (well spacing) *

* SystemC 2.1.1 --- Dec 20 2010 23:17:37 * Copyright (c) 1996-2010 by all Contributors * ALL RIGHTS RESERVED

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES

11

* Diffusion * r201 = 4 r202 = 4 r203 = 6 r204 = 6 r210 = 16 * * Poly * r301 = 2 r302 = 2 r303 = 4 r304 = 3 r305 = 1 r306 = 4 r307 = 3 r310 = 16 * * Contact r401 = 2 r402 = 4 r403 = 1 r404 = 1 r405 = 1 r406 = 2 r407 = 1 * metal r501 = 3 r502 = 4 r510 = 16 * via r601 = 2 r602 = 4 r604 = 1 r605 = 1 * metal2 r701 = 3 r702 = 4 r710 = 16

N+, P+ (diffusion width) (diffusion spacing) (border of nwell on diffp) (nwell to next diffn) (minimum diff surface lambda2)

not inv_3(w5,D); nor nor2_4(Q,Qbar,w6); nor nor2_5(Qbar,w4,Q); endmodule

A PPENDIX E G ATED D L ATCH WITH Enable C ONTROL , CMOS V ERILOG

module Q1132( D,En,Qbar,Q); input D,En; output Qbar,Q; wire w4,w5,w6,w8,w9; reg vdd=1; reg vss=0; nmos nmos_1(Qbar,vss,Q); // 1.0u 0.12u nmos nmos_2(Q,vss,Qbar); // 1.0u 0.12u pmos pmos_3(w4,vdd,Q); // 2.0u 0.12u pmos pmos_4(Q,w5,w6); // 2.0u 0.12u pmos pmos_5(Qbar,w4,D); // 2.0u 0.12u nmos nmos_6(Q,w8,w6); // 1.0u 0.12u pmos pmos_7(w5,vdd,Qbar); // 2.0u 0.12u nmos nmos_8(Qbar,w9,D); // 1.0u 0.12u pmos pmos_9(Q,w5,En); // 2.0u 0.12u not inv_10(w6,D); nmos nmos_11(w9,vss,En); // 1.0u 0.12u nmos nmos_12(w8,vss,En); // 1.0u 0.12u pmos pmos_13(Qbar,w4,En); // 2.0u 0.12u endmodule

(poly width) (gate length) (high voltage gate length) (poly spacing) (spacing poly and unrelated diff) (width of drain and source diff) (extra gate poly) (Minimum poly surface lambda2)

(contact width) (contact spacing) (metal border for contact) (poly border for contact) (diff border for contact) (contact to gate) (poly2 border for contact) (metal width) (metal spacing) (metal surface lambda2) (Via width) (Spacing) (border of metal) (border of metal2) (Metal 2 width) (spacing) (Metal2 surface lambda2)

A PPENDIX F B ISTABLE C IRCUIT, CMOS V ERILOG

module Q1134( A,Abar); input A; output Abar; reg vdd=1; reg vss=0; pmos pmos_1(Abar,vdd,A); nmos nmos_2(A,vss,Abar); nmos nmos_3(Abar,vss,A); pmos pmos_4(A,vdd,Abar); endmodule

A PPENDIX C BASIC D L ATCH , CMOS V ERILOG

module Q1130( D,Q,Qbar); input D; output Q,Qbar; wire w4,w5,w6; nmos nmos_1(Qbar,vss,Q); // 1.0u 0.12u nmos nmos_2(Q,vss,Qbar); // 1.0u 0.12u pmos pmos_3(w4,vdd,Q); // 2.0u 0.12u pmos pmos_4(Q,w5,w6); // 2.0u 0.12u pmos pmos_5(out2,w4,D); // 2.0u 0.12u nmos nmos_6(Q,vss,w6); // 1.0u 0.12u pmos pmos_7(w5,vdd,Qbar); // 2.0u 0.12u nmos nmos_8(Qbar,vss,D); // 1.0u 0.12u not inv_9(w6,D); endmodule

// // // //

2.0u 1.0u 1.0u 2.0u

0.12u 0.12u 0.12u 0.12u

A PPENDIX G B ISTABLE C IRCUIT WITH L OADING C ONTROL , CMOS V ERILOG

module Q1134m( D,C,Qbar); input D,C; output Qbar; wire w2,w4,w5; reg vdd=1; reg vss=0; pmos pmos_1(Qbar,vdd,w2); // 2.0u 0.12u nmos nmos_2(w5,w2,w4); // 1.0u 0.12u nmos nmos_3(w5,vss,Qbar); // 1.0u 0.12u nmos nmos_4(Qbar,vss,w2); // 1.0u 0.12u pmos pmos_5(w5,vdd,Qbar); // 2.0u 0.12u not inv_6(w4,C); nmos nmos_7(w2,D,C); // 1.0u 0.12u endmodule

A PPENDIX D G ATED D L ATCH WITH Enable C ONTROL , G ATE L EVEL V ERILOG

module Q1131( En,D,Q,Qbar); input En,D; output Q,Qbar; wire w4,w5,w6; and and2_1(w4,En,D); and and2_2(w6,w5,En);

A PPENDIX H C2 MOS S TATIC D L ATCH , CMOS V ERILOG

module Q1138a( clk,D,Q); input clk,D; output Q; reg vdd=1;

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GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

reg vss=0; wire w3,w4,w5,w8,w9,w10; not inv_1(w3,clk); nmos #(3.1) nmos_2(w5,w4,w3); // 1.0u 0.12u nmos #(1.0) nmos_3(w4,vss,D); // 1.0u 0.12u pmos #(1.0) pmos_4(w8,vdd,D); // 2.0u 0.12u pmos #(3.1) pmos_5(w5,w8,clk); // 2.0u 0.12u not inv_6(Q,w5); pmos #(1.0) pmos_7(w9,vdd,Q); // 2.0u 0.12u nmos #(1.0) nmos_8(w10,vss,Q); // 1.0u 0.12u pmos #(3.1) pmos_9(w5,w9,w3); // 2.0u 0.12u nmos #(3.1) nmos_10(w5,w10,clk); //1.0u 0.12u endmodule

ACKNOWLEDGMENT The authors would like to thank their teachers, instructors and TAs without whom this work would neither have been required, nor completed. In particular, they would like to thank Dr. Bazaz for an invigorating introduction to the world of VLSI design, and Mr. Kashif Riaz for being his invaluable aide. R EFERENCES
[1] J. P. Uyemura, Introduction to VLSI Circuits and Systems. Georgia Instiute of Technology, USA: Wiley, Inc., 2002. [2] (2010, Dec) [internal giki subsite only] ee424: List of assigned term projects. GIK Institute, Topi, Pakistan. [Online]. Available: http://192.168.1.32/le.php/13/Term_Projects_ASIC_Design_.pdf [3] Electronic design. Hayden Pub. Co., 1988, no. v. 36, nos. 23-29. [Online]. Available: http://books.google.com/books?id=oM4EAQAAIAAJ [4] (2010, Dec) Microwind - about us. Department of Electrical and Computer Engineering, INSA, Toulouse. [Online]. Available: http://www.microwind.net/about_us.php [5] (2010, Dec) Bsim homepage introduction. University of California, Berkeley. [Online]. Available: http://wwwdevice.eecs.berkeley.edu/bsim3/bsim4_intro.html [6] (2010, Dec) About osci - open systemc initiative (osci). The Open SystemC Initiative (OSCI). [Online]. Available: http://www.systemc.org/about

A PPENDIX I C2 MOS DYNAMIC D L ATCH , CMOS V ERILOG

module Q1138b(D,clk,Q); input D,clk; output Q; wire w2,w3,w7,w8,w9,w10; reg vdd=1; reg vss=0; nmos #(10) nmos_1(w3,vss,w2); // 1.0u 0.12u nmos #(17) nmos_2(Q,w3,clk); // 1.0u 0.12u not #(17) inv_3(w7,clk); pmos #(10) pmos_4(w8,vdd,w2); // 2.0u 0.12u pmos #(17) pmos_5(Q,w8,w7); // 2.0u 0.12u nmos #(31) nmos_6(w2,w9,w7); // 1.0u 0.12u pmos #(10) pmos_7(w10,vdd,D); // 2.0u 0.12u nmos #(10) nmos_8(w9,vss,D); // 1.0u 0.12u pmos #(31) pmos_9(w2,w10,clk); // 2.0u 0.12u capa #(1) Capa_10(vss,w2); // 1pF endmodule