1

CPLD
CPLD Complex Programmable Logic Device
Combination Sequential
JTAG Programmer

GAL (GAL : Gate Array Logic)

Combination


PAL (PAL : Programmable Array Logic)
GAL Logic gate Flip flop
Combination logic Sequential logic
I/O

CPLD
HDL Flash
20 40 10000 I/O

800 Flip-flop 36
Flip-flop
FPGA (FPGA : Filled Programmable Gate Array)

(CPU) Flip-flop
I/O
Volantine RAM
Flash memory
Config. Flash
Config. Flash
FPGA

2
CPLD CPLD FPGA

CPLD XC9500 XILINX

CPLD

1. CPLD 125 MHz 5 V 3.3 V

2. I/O 24 mA Sink Source
3. CPLD I/O Package Table 2
4. CPLD Table 1
(Usable Gates) Register Flip-flop

5. 5 V (a)
3.3 V (b) VCCINT VCCIO

4
CPLD
CPLD XC9500 XILINX
Function Blocks (FBs) I/O Blocks (IOBs)
Fast CONNECT switch matrix F
In-System
Programming Controller Fast CONNECT switch matrix Function
Blocks CPLD
Function Block Fast CONNECT
switch matrix 36 18 Function Block
Macrocells 18 Macrocell
-
I/O Blocks I/O
Input / Output Bi-direction Slew rate

1 CPLD XC9500 XILINX

5
Function Block
Function Block Macrocell 18
Combination Logic
Sequential Logic Programmable AND-Array Fast
CONNECT switch matrix True complement 72
Product Term Allocators Macrocell 18 2

2 Function Block
Macrocell
Macrocell Function Block
Product Term 5 AND-Array
( OR XOR Gates) Combination
Register Clock, Set / Reset Enable
Macrocell register -
D-Flip-flop, T-Flip-flop Combination
Set/Reset - Synchronous

6
Asynchronous operation Individual Global operation
- (

3 Macrocell CPLD XC 9500

4 Global
Macrocell

7
Fast CONNECT Switch Matrix
Fast CONNECT Switch Matrix Function Block
(FB) Function Block Fast CONNECT Switch Matrix 36
Fast CONNECT Switch Matrix Wired-AND
Function Block

5 Fast CONNECT Switch Matrix

I/O Block
I/O Block (IOB) Macrocell I/O
I/O Block 5 Input Buffer
I/O CPLD Output Buffer

8
I/O CPLD Slew Rate Global
Tri-state (GTS) Output Enable (OE) Product Term
I/O Pull-up Resistor VCCIO I/O
Pull-up High UserProgrammable Ground I/O

6 I/O Block Global Tri-State

9
CPLD
CPLD XC9500
In System Programming Protocol JATAG 4
IEEE 1149.1 Boundary-Scan (JTAG)
10000

CPLD XC9500
read security bits write security bits
6
JTAG Program

6
( Power- Up Characteristics )
CPLD XC9500 5 V
CPLD
(Safe Level Voltage) 3.8 V Pull-Up Resister
(Initialized)
100 - 300
XC9536 XC95288

10

7 ( Power- Up Characteristics )

( Development System Support)

CPLD XC9500
XILINX Foundation XILINX Web Pack
Schematic ABEL-HDL VHDL
Verilog State Diagram
ABEL-HDL

module mygate1
Title 'mygate1'
Declarations
A PIN;
B PIN;
EN PIN;
AND_OUT
OR_OUT
NOT_A
SUM_OUT
C_OUT

PIN istype 'com';

PIN istype 'com';
PIN istype 'com';
PIN istype 'com';
PIN istype 'com';

Equations
AND_OUT = A & B;
OR_OUT
= A # B;
NOT_A
= !A;
SUM_OUT = A $ B;
C_OUT
= A&B;
end mygate1

8 ABEL-HDL

11
- 4 to 1 multiplexer design with case construct
SEL: in STD_LOGIC_VECTOR(1 downto 0);
A, B, C, D:in STD_LOGIC;
MUX_OUT: out STD_LOGIC;
process (SEL, A, B, C, D)
begin
case SEL is
when "00" => MUX_OUT <= A;
when "01" => MUX_OUT <= B;
when "10" => MUX_OUT <= C;
when "11" => MUX_OUT <= D;
end case;
end process;

9 VHDL

10 State Diagram