19

1. XILINX Foundation
XILINX Foundation ver 2.1i ICON

Foundation
1.1 Getting Started 2 Open an Existing Project (
) Create a New Project Create a
New Project 1 OK
1. Project

2.

1 Getting Start

2 New Project

1.2 New Project 2 OK

1.3 Project Manager 3

3 Project Managet

20

Project Manager Foundation

Design Entry
Design Entry 3

- Schematic Editor Schematic Diagram

- HDL Editor
HDL
VHDL Verilog Abel HDL

- FSM Editor

State Diagram


2. (Schematic Design Techniques)

(Schematic Editor)

2.1 Schematic Editor Schematic Editor

Project Manager 4

4 Schematic Editor

Schematic Editor 5

5
Schematic Editor

Windows Tools
Simulation Tools
Schematic Tools

21

Schematic Tools Tool bar Schematic Diagram

6
Hierachy Push / Pop menu
Symbol Tool box
Tool bar
Tool bar
Tool bar
Tool bar
Tool bar Hierachy
Tool bar

6 Schematic Tool bars

2.2
ANDGate OR-Gate 7
7

1. Symbol Tool box Logic Symbol Library

Symbol

Symbol

22

2. AND2 OR2
3. IBUF, IPAD, OBUF OPAD
( 4 I/O
CPLD )
4. Draw wires
8

8
5. IPAD OPAD I/O
CPLD
9 10

9 Symbol Properties

10 Symbol Properties

23

2
I/O CPLD LED AND-Gate
OR-Gate I/O CPLD I/O
IPAD OPAD

1.

3. Add

2. I/O
5. OK
4. Apply

11 IPAD OPAD
I/O

3. Change
2.
1.

5. OK

4. Apply

12 IPAD OPAD

24

13 I/O
6. Save
8. Project Manager
9. Implementation CPLD

14

Implementation

14.1 Implementation

25

10. CPLD
Programming

15

JTAG Programming
Implementation CPLD
16 Operations

16 JTAG Programmer

17 JTAG Programmer

26

Program Erase Before Programming OK

18 Options

CPLD

3. Schematic Diagram

BCD to 7-Segment
Decade counter
Library Table

Library Table

19

27

1. Schematic Diagram
Hierachy Connector 20

Hierachy
Connector

20 Schematic Diagram
20 Save
2. Hierachy 21

21 Hierachy
1. 8
2.
3. OK

22

28

OK Sheet Library
? 23 No
Library Table Sheet File -> New Sheet
Library Table EXP1
24

23

Library

24

Sheet 25

25

29

3.
Library Table
Hierachy Push/Pop 26

1.
2.

3.

Save

26
CPLD
IBUF, IPAD, OBUF IPAD Hierachy Connector 27

27 Hierachy Connector

30

4. ( Logic Circuit Simulations)

Library Table
2
-
-
Simulation Logic Probe
Function Generator
1 27
A B
output 3
Simulation

1.

2.
Logic Probe
input output

3.
SIM

28 Logic Probe
Logic Probe SIM 3
Logic Simulator 29

31

4. Select Simulator

29 Logic Simulator

7. A B
5. A
6. z A

30 Stimulator Selection

32

30 z A
B x B (
)
A B
z x Logic Probe A B
0 1 31

8.

31 Simulation
31 8 Logic Probe
32 Simulation A B
z x

Logic Probe

33

32 Simulation
5. (Sequencial Logic Circuit)
-
Counter Shift register (Clock)
Simulation (Combination
Logic Circuit)
2 4Bit Cascade Binary Counter
CB4CE Table

33 4-bit binary counter Logic Probe

34

Logic Probe
Simulation Logic Probe

Waveform Viewer

34 Waveform Viewer

Stimulator
1 1
Clock Counter C
3. Sim. step 10 nS

clock 1 1

1. C
2. B0

1 00MHz

35 Clock Counter module

35

Stimulator Selection
1 CE 0 CLR

36

Simulation
period

36

Simulation step
Clock
Simulation period 5 nS on period
10 nS 1

36

6.
Schematic Diagram
Data bus, Address bus


Data Counter CB4CE
37
1.

3.

1.

2.

4.

Add Bus
End..

37
2.

Edit Bus
38

37

1.

2.

3.

Tap

38

3. Tap

39
1.

6. 4
2.

3. Q3

Q0
4.

39 Tap

5. BUF4

38

4. Tap
Tap - 39
Tap Tap

QBUS3 QBUS1 QBUS1 QBUS3
Tap BUF4