59

7. State Diagram
State Diagram
(Sequential Logic Circuit) (Clock Signal)
Node State Diagram

State Diagram
HDL
HDL
State Diagram
State Equations State Equation
(Subroutines)
State Equations State Machine
Machine
7.1 State Diagram Editor State Diagram

State
Tool
bars

State Editor

60
7.2 State Tool bars
Tool bar State
Tool bar Transistion
Tool bar Condition
Tool bar Entry Action
Tool bar State Action
Tool bar Exit Action
Tool bar Transistion Action
Tool bar Diagram Action
Tool bar
Tool bar Node
Tool bar
Tool bar
Tool bar (Bi-direct port)
7.3 State Diagram

Output ports

Signal
Node

Input ports

Condition

Transistion Action

Transistion

State

State Action

61
State Diagram D Latch State Diagram

7.4 State Diagram

diagram name 8

diagram action (varibles ) port outputs

port
I/O input ports output
ports
input port
output port
bi-directional -

62
machine name State Machine
Machine 2 State
-
variable / signal node
State node
stage counter
cnt[3:0]
state

subroutine
actions

4
- transistion action
state
- entry action

state
- state action

state
- exit action

state
condition

state
transistion

state
reset
reset

63
State Equations Graphic Tool State Diagram Editor
State Equations
Xilinx Foundation Ver.2.1i State Diagram
Editor Graphic Tool State Equations State
Diagram
HDL
J-K Flip-Flop State Diagram HDL
Design Wizard
1.

2. I/O JK Flip-flop
- Flip-flop Output Clock Negative falling
edges Output Q NQ
- Q output 1 J = 1 K = 0
- Q output 0 J = 0 K = 1
- Q output ( toggle) Clock J = 1 K = 1
- Q output Clock J = 0 K = 0
3. HDL Design wizard State Diagram Editor
- Project Manager

1.

64

2.
3. OK
4. Next
7.
5. ABEL
8. Next

6. Next

9. I/O
10. CLK
Clock Advanced
Q NQ
Registered

11. Next

12. One
13. Finish

65
- 13 State Diagram Editor
State Diagram JK Flip-Flop

State Diagram JK Flip-flop

-
- State S1 S2
1.
3.

2.

4.

66
- State Action State S1 S2 Output Q NQ

1.

2.

3.

- Transistion 4
4. 2

1.

3.

2.

-
1.
3.

2.

67
- Condition Transistion
4 Save
3. State

2.

1.

- Transistion Action Transistion

2.
Action

1.

- Syntax Generate
Code ABEL - HDL Check Syntax
1.
2.

3.

68
ABEL HDL State Diagram
" File: C:\FNDTN\ACTIVE\PROJECTS\EXPX12\JKFF.abl
" created:
03/15/06 14:11:41
" from: 'C:\FNDTN\ACTIVE\PROJECTS\EXPX12\JKFF.asf'
" by:
fsm2hdl - version: 2.0.1.53
"
module jkff
Title 'jkff'
Declarations
"clocks
CLK PIN;
"input ports
CLR PIN;
J PIN;
K PIN;
"output ports
NQ PIN istype 'reg';
Q PIN istype 'reg';
Declarations
cnt1..cnt0 NODE istype 'reg';
cnt = [cnt1..cnt0];
"******** SYMBOLIC state machine: Sreg0 ******
Sreg0 STATE_REGISTER;
S1, S2 STATE;
"diagram ACTIONS
"************* state machine: Sreg0 *************
Equations
" clock signals definitions
Sreg0.clk = CLK;
NQ.clk=CLK;
Q.clk=CLK;
cnt.clk=CLK;
State_diagram Sreg0
ASYNC_RESET S1 : CLR;

69
State S1:
Q := '0';
NQ := '1';
IF ((K & J & !CLR & (cnt == 0))#(!K &J)) THEN
S2 WITH
cnt := 1;
ENDWITH
ELSE S1;
State S2:
Q := '1';
NQ := '0';
IF ((K & J & (cnt == 1)) # CLR#(K & !J)) THEN
S1 WITH
cnt := 0;
ENDWITH
ELSE S2;
" end of state machine - Sreg0
end jkff

- HDL Code
1.

2.

3.
OK

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- HDL Code JK Flip-flop

1.

2.

3.
OK

- JK Flip flop Library Table

State Diagram Schematic Editor

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- Hierachy
State Diagram Editor
D-Latch
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