Solutions to Homework 3 Problems ELEC 7250 VLSI Testing (Spring 2004)

March 2, 2004

Problem 5.4
The longest path in the circuit (see Figure 5.2) is C0 to C4. The delay of this path should be tested for both rising and falling transitions. As shown in Example 5.3, the path delay for a rising transition is tested by vector 2 followed by 6, which causes the transition to ripple through the path. Similarly, the path delay for a falling transition can be tested by vector-pair, 6 followed by 2. From Table 5.2, vectors 1 through 6 cover all stuck-at faults. Since the circuit is combinational, these vectors can be applied in any order. We construct a sequence of seven vectors using these six vectors that contains the two delay test vector-pairs. The sequence is 1, 2, 6, 2, 3, 4, 5. Note: If we use the result of Table 5.3, a sequence of six vectors for all stuck-at faults and two path delay faults can be constructed.

Problem 5.10
With the given inputs, 00, and output X , when the clock is applied the circuit will not be initialized. The reason is that in a three-state logic system the inversion of X is also X . The circuit can be initialized to a 1 output by clocking the ip- op when a 11 input is applied. Then, if we change the input to 10 and clock the ip- op, the output will become 0. These two vectors can be correctly simulated by a three-state logic simulator.

Problem 5.25 Fault sampling

Since the size of fault population (Np = 105) is very large compared to the sample size (Ns = 4 000), we use the approximation of Equation 5.5 (page 123 in the book.) 900 Sample coverage x = 3 000 = 0:975 4
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Using Equation 5.8 (see page 123 in the book), we get q 3 coverage estimate = x 4:5 1 + 0:44N x(1 ; x)
Ns

:5 p = 0:975 4 4000 1 + 0:44 4 000 0:975 0:025 = 0:975 0:0075 or 97:50 0:75 percent

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