1

POD-A

R19

18K0

Range Buffer
A+5

x(4.583) Gain Buffer

A+5

(4.8298)

optional HF compensation
3

R20

4K7

v+

U14 MAX477
6

**

v+

U15 AD8048
6

1.20Vpp ** R38 220R

3

20K X5

OMIT fot ADC 5540

ADC Buffer
(1.6667)
A+5 F

C56

0->20pF

v+

U16 MAX477
6

**

2.00Vpp

POD-B

20K X5
(4.8298)
E

R22

18K0

v-

v-

v-

C57 0->20pF optional HF compensation

D5
A-5 A-5 4 4

D6
A-5 4

R37 430R R35 120R

1N4148

1N4148

R40 220R R39 330R HF Filter R51 1K0 C39

E

R23

4K7

Logic Pod

U18 INPUT BUFFERS 1:1 R29 220R

12 14 15 11 1 5 2 4 6 10 9 X0 X1 X2 X3 Y0 Y1 Y2 Y3 INH A B X Y VDD VSS 13 3 16 8 A+5

C37 104 RV1 4K7 ZERO SET TP5-TP4 =0.0V

104

2:1
D

R30 220R R31

VCC

Vertical Input
C

SIG-A

220R C52 R32 5:1 (5.273) C69 470R cspeed 104

GND

VEE

A-5

A-5 CNT-2

MAX4052

Range Select

optional HF compensation

R33

Buffers

110R
SIG-B

TP3-TP4 =1.0V
DIV64

TP3
A+5

TP4

TP5 U13
14 15 A-IN VCCA

Analogue Source
U17
12 14 15 11 BNC-B BNC-A POD-B POD-A 1 5 2 4 6 10 9 X0 X1 X2 X3 Y0 Y1 Y2 Y3 INH A B X Y VDD VSS 13 3 16 8

ADC-5540
D8 D7 D6 D5 D4 D3 D2 D1 CLK 4 5 6 7 8 9 10 21 18 20 19 3 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ZZ-CLK STOR

SCALE ADJUST

bs11-5.sch

RV2
A+5

24

CNT-1 B

C40 500R 104

C41 104

C42 + 10uF

VRT VRM VRB

C43 104

1 23

13 VEE 7 A-5 A-5

OE OE VEE OVER

CH-A
VCC

CH-B
VCC

CH-C
VCC

CH-D
VCC

MAX4052

* BNC/Pod

ADC Module * SOCKET for ADC Adapter

LD3 YEL

LD4 YEL

LD5 YEL

LD6 YEL

CH-A/B

A+5 POD-B POD-A BNC-B BNC-A A

R41 + 1K0 * NOTE:- 74HC4052 is suitable alternative for MAXIM part CMOS 4052 will result in degraded performance

C44 1uF

C46 104 C47 104

C48 104 C49 104

C50 104 C51 104

A-5

Flash ADC
BitScope Designs
Title
A3
BitScope Analog Capture
A

SAMPLE
(C) 2000 BitScope Designs
1 2 3

C45 + 1uF

** NOTE:- Pin compatible OP AMPS (TL071) will result in low BW (<4MHz) signal path

Document Number PCB 11

23-Aug-2000
8

Date:

Q5 BC558

C38

10uF

C27 100pF

RNG1 RNG0

PG0 PG1 EVENT C

AD[0..7]

AD[0..7]

JP3
VCC 1 2 3

MC10319 SMT ADC

zz-clk
Default short 2-3
ZZ-CLK* ZZ-CLK B

STOR

Sheet 4 of 5
Rev 1.1

BS11-4.SCH
9