CD4016BC Quad Bilateral Switch

November 1983 Revised January 1999

CD4016BC Quad Bilateral Switch

General Description
The CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066BC. s Extremely high control input impedance: 1012 (typ.) s Low crosstalk between switches: 50 dB (typ.) @ fIS = 0.9 MHz, RL = 1 k s Frequency response, switch ON: 40 MHz (typ.)

Features
s Wide supply voltage range: 3V to 15V s Wide range of digital and analog switching: 7.5 VPEAK s ON resistance for 15V operation: 400 (typ.) s Matched ON resistance over 15V signal input: RON = 10 (typ.) s High degree of linearity: 0.4% distortion (typ.) @ fIS = 1 kHz, VIS = 5 Vp-p, VDDVSS = 10V, RL = 10 k s Extremely low OFF switch leakage: 0.1 nA (typ.) @ VDD VSS = 10V TA = 25C

Applications
Analog signal switching/multiplexing Signal gating Squelch control Chopper Modulator/Demodulator Commutating switch Digital signal switching/multiplexing CMOS logic implementation Analog-to-digital/digital-to-analog conversion Digital control of frequency, impedance, phase, and analog-signal gain

Ordering Code:
Order Number CD4016BCM CD4016BCN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the letter suffix X to the ordering code.

Connection Diagram
Pin Assignments for DIP and SOIC

Schematic Diagram

1999 Fairchild Semiconductor Corporation

DS005661.prf

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CD4016BC

Absolute Maximum Ratings(Note 1)

(Note 2) VDD Supply Voltage VIN Input Voltage TS Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) 260C 700 mW 500 mW 0.5V to +18V 0.5V to VDD + 0.5V 65C to + 150C

Recommended Operating Conditions (Note 2)

VDD Supply Voltage VIN Input Voltage TA Operating Temperature Range 3V to 15V 0V to VDD 40C to +85C

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 2)

Symbol IDD Parameter Quiescent Device Current Signal Inputs and Outputs RON ON Resistance RL = 10k to (VDD V SS)/2 VC = VDD, VIS = VSS or VDD VDD = 10V VDD = 15V RL = 10k to (VDD V SS)/2 VC = VDD VDD = 10V, VIS = 4.75 to 5.25V VDD = 15V, VIS = 7.25 to 7.75V RON ON Resistance Between any 2 of 4 Switches (In Same Package) IIS Input or Output Leakage Switch OFF Control Inputs VILC LOW Level Input Voltage VIS = VSS and VDD VOS = VDD and VSS IIS = 10 A VDD = 5V VDD = 10V VDD = 15V VIHC HIGH Level Input Voltage VDD = 5V VDD = 10V VDD = 15V (Note 3) and Figure 8 IIN Input Current VCC VSS = 15V VDD VIS VSS VDD VC VSS
Note 3: If the switch input is held at VDD, VIHC is the control input level that will cause the switch output to meet the standard B series VOH and IOH output levels. If the analog switch input is connected to VSS, VIHC is the control input level which allows the switch to sink standard B series |IOH|, high level current, and still maintain a VOL B series. These currents are shown in Figure 8.

Conditions VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS

40C Min Max 1.0 2.0 4.0 Min

25C Typ 0.01 0.01 0.01 Max 1.0 2.0 4.0

+85C Min Max 7.5 15 30

Units A A A

610 370

275 200

660 400

840 520

1900 790

850 400

2000 850

2380 1080

RL = 10k to (VDD V SS)/2 VC = VDD, VIS = VSS to VDD VDD = 10V VDD = 15V VC = 0, VDD = 15V VIS = 0V or 15V, VOS = 15V or 0V 50 15 10 0.1 50 200 nA

0.9 0.9 0.9 3.5 7.0 11.0 0.3 3.5 7.0 11.0 105

0.7 0.7 0.7 3.5 7.0 11.0 0.3

0.4 0.4 0.4

V V V V V V

1.0

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CD4016BC

AC Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay Time Signal Input to Signal Output

(Note 4)
Conditions VC = VDD, CL = 50 pF, (Figure 1) RL = 200k VDD = 5V VDD= 10V VDD = 15V 58 27 20 20 18 17 15 11 10 0.4 100 50 40 50 40 35 40 25 22 ns ns ns ns ns ns ns ns ns % Min Typ Max Units

TA = 25C, tr = tf = 20 ns and VSS = 0V unless otherwise specified

tPZH, tPZL

Propagation Delay Time Control Input to Signal Output HIGH Impedance to Logical Level

RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3) VDD = 5V VDD = 10V VDD = 15V RL = 1.0 k, CL = 50 pF, (Figure 2, Figure 3) VDD = 5V VDD = 10V VDD = 15V VC = VDD = 5V, VSS = 5 RL = 10 k, VIS = 5 VP-P, f = 1 kHz, (Figure 4)

tPHZ, tPLZ

Propagation Delay Time Control Input to Signal Output Logical Level to HIGH Impedance Sine Wave Distortion

Frequency Response Switch ON (Frequency at 3 dB)

VC = VDD = 5V, VSS = 5V, RL = 1 k, VIS = 5 VP-P, 20 Log10 V OS/VOS (1 kHz) dB, (Figure 4)

40

MHz

Feedthrough Switch OFF (Frequency at 50 dB)

VDD = 5V, VC = VSS = 5V, RL = 1 k, VIS = 5 VP-P, 20 Log10 (VOS/VIS) = 50 dB, (Figure 4)

1.25

MHz

Crosstalk Between Any Two Switches (Frequency at 50 dB)

VDD = VC(A) = 5V; VSS = VC(B) = 5V, RL = 1 kVIS(A) = 5 VP-P, 20 Log10 (VOS(B)/VOS(A) ) = 50 dB, (Figure 5)

0.9

MHz

Crosstalk; Control Input to Signal Output Maximum Control Input

VDD = 10V, RL = 10 k RIN = 1 k, VCC = 10V Square Wave, CL = 50 pF (Figure 6) RL = 1 k, CL = 50 pF, (Figure 7) VOS(f) = VOS(1 kHz) VDD = 5V VDD = 10V VDD = 15V

150

mVP-P

6.5 8.0 9.0 4 4 0.2 5 7.5

MHz MHz MHz pF pF pF pF

CIS COS CIOS CIN

Signal Input Capacitance Signal Output Capacitance Feedthrough Capacitance Control Input Capacitance VDD = 10V VC = 0V

Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: These devices should not be connected to circuits with the power ON. Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified. Note 7: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input.

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CD4016BC

AC Test Circuits and Switching Time Waveforms

FIGURE 1. tPLH, tPLH Propagation Delay Time Control to Signal Output

FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output

FIGURE 3. tPZH, tPHZ Propagation Delay Time Control to Signal Output

VC = VDD for distortion and frequency response tests VC = VSS for feedthrough test

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough

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CD4016BC

AC Test Circuits and Switching Time Waveforms

(Continued)

FIGURE 5. Crosstalk Between Any Two Switches

FIGURE 6. Crosstalk Control to Input Signal Output

FIGURE 7. Maximum Control Input Frequency

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CD4016BC

AC Test Circuits and Switching Time Waveforms

Temperature Range VDD 5 5 COMMERCIAL 10 10 15 15 VIS 40C 0 5 0 10 0 15 0.2 0.2 0.5 0.5 1.4 1.4 Switch Input IIS (mA) 25C 0.16 0.16 0.4 0.4 1.2 1.2

(Continued) Switch Output VOS(V) +85C 0.12 0.12 0.3 0.3 1.0 1.0 13.5 9.5 1.5 4.6 0.5 Min Max 0.4

FIGURE 8. CD4016B Switch Test Conditions for VIHC

Typical Performance Characteristics

ON Resistance vs. Signal Voltage TA = 25C ON Resistance Temperature Variation for VDD VSS = 10V

ON Resistance Temperature Variation for VDD VSS = 15V

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CD4016BC

Typical Applications
4 Input Multiplexer

Sample/Hold Amplifier

Special Considerations The CD4016B is composed of 4, two-transistor analog switches. These switches do not have any linearization or compensation circuitry for R ON as do the CD4066B's. Because of this, the special operating considerations for the CD4066B do not apply to the CD4016B, but at low supply voltages, 5V, the CD4016B's on resistance becomes non-linear. It is recommended that at 5V, voltages on the in/ out pins be maintained within about 1V of either VDD or VSS; and that at 3V the voltages on the in/out pins should be at VDD or VSS for reliable operation.

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CD4016BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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CD4016BC Quad Bilateral Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

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