ISEM Reference Card (Integer Unit)

 Notation  Load Instructions

Notation Meaning Assembler Syntax
reg integer register (%r0{%r31); subscript de- operation [address ], reg rd
notes instruction eld (e.g., reg rd ) operation a [regaddr ]asi , reg rd
const unsigned integer value; subscript denotes
size in bits (e.g., const 22) Instruction Formats
disp signed integer displacement; subscript de- 31:30 29:25 24:19 18:14 13 12:5 4:0
notes size in bits (e.g., disp 22) 11 rd op3 rs1 0 asi rs2
siconst 2's complement signed integer value; sub- 11 rd op3 rs1 1 siconst13
script denotes size in bits (e.g., siconst 30)
address reg rs1 Operations
reg rs1 + reg rs2 operation
reg rs1 + siconst 13 operation op3 (alt. space) op3
reg rs1 ; siconst 13 ldsb 001001 ldsba 011001
siconst 13 ldsh 001010 ldsha 011010
siconst 13 + reg rs1 ldub 000001 lduba 010001
regaddr reg rs1 lduh 000010 lduha 010010
reg rs1 + reg rs2 ld 000000 lda 010000
label an instruction label ldd 000011 ldda 010011
asi address space identier (0 to 255)
ldstub 001101 ldstuba 011101
 Registers swap 001111 swapa 011111
Name
%r0{%r31
Meaning
integer registers
 SETHI Instructions
%g0{%g7 global regs (%r0{%r7) Assembler Syntax
%o0{%o7 output regs (%r8{%r15) sethi const 22, reg rd
%l0{%l7 local regs (%r16{%r23) sethi %hi(const ), reg rd
%i0{%i7 input regs (%r24{%r31) Instruction Format
%fp frame pointer (%i6) 31:3029:25 24:22 21:0

%sp stack pointer (%o6) 00 rd 100 const22

%asr1{%ars31 ancillary state registers
%psr processor status register  Arithmetic and Logical Instructions
%tbr trap base register Assembler Syntax
%y multiply/divide register operation reg rs1 , reg rs2 , reg rd
%r0 always holds the 32-bit integer value 0. operation reg rs1 , siconst 13, reg rd
%psr has the following structure:
31:28 27:24 23 22 21 20 19:14 13 12 11:8 7 6 5 4:0
Instruction Formats
31:30 29:25 24:19 18:14 13 12:5 4:0
impl ver n z v c reserved EC EF PIL S PS ET CWP op3
10 rd rs1 0 unused (zero) rs2
%tbr has the following structure:
31:12 11:4 3:0
10 rd op3 rs1 1 siconst13
Trap base address trap type 0000
Operations
operation op3 operation op3
 Store Instructions add 000000 addcc 010000
Assembler Syntax addx 001000 addxcc 011000
operation reg rd , [address ] and 000001 andcc 010001
operation a reg rd , [regaddr ]asi andn 000101 andncc 010101
Instruction Formats or 000010
mulscc
orcc
100100
010010
31:30 29:25 24:19 18:14 13 12:5 4:0
11 rd op3 rs1 0 asi rs2 orn 000110 orncc 010110
udiv 001110 udivcc 011110
11 rd op3 rs1 1 siconst13 umul 001010 umulcc 011010
sdiv 001111 sdivcc 011111
Operations smul 001011 smulcc 011011
operation op3 operation op3 sub 000100 subcc 010100
(alt. space) subx 001100 subxcc 011100
stb 000101 stba 010101 taddcc 100000 taddcctv 100010
sth 000110 stha 010110 tsubcc 100001 tsubcctv 100011
st 000100 sta 010100 xor 000011 xorcc 010011
std 000111 stda 010111 xnor 000111 xnorcc 010111

1
 Shift Instructions  Restore and Save Instructions
Assembler Syntax Assembler Syntax
operation reg rs1 , reg rs2 , reg rd operation reg rs1 , reg rs2 , reg rd
operation reg rs1 , const 5, reg rd operation reg rs1 , siconst 13, reg rd
Instruction Formats Instruction Formats
31:30 29:25 24:19 18:14 13 12:5 4:0 31:30 29:25 24:19 18:14 13 12:5 4:0
10 rd op3 rs1 0 unused (zero) rs2 10 rd op3 rs1 0 unused (zero) rs2
10 rd op3 rs1 1 unused (zero) const5 10 rd op3 rs1 1 siconst13

Operations Operations
operation op3 operation op3
sll 100101 restore 111101
sra 100111 save 111100
srl 100110
 Trap Instructions
 Branch Instructions Assembler Syntax
Assembler Syntax operation reg rs1 , reg rs2 , reg rd
operation label operation reg rs1 , siconst 13, reg rd
operation ,a label
Instruction Formats
Instruction 24:22
31:30 29 28:25
Format 21:0
31:30 29 28:25 24:19 18:14 13 12:5 4:0
10 r cond 111010 rs1 0 unused (zero) rs2
00 a cond 010 disp22
10 r cond 111010 rs1 1 siconst13
Operations
operation cond operation cond Operations
bn 0000 ba 1000 operation cond operation cond
be (bz) 0001 bne (bnz) 1001 tn 0000 ta 1000
ble 0010 bg 1010 te (tz) 0001 tne (tnz) 1001
bl 0011 bge 1011 tle 0010 tg 1010
bleu 0100 bgu 1100 tl 0011 tge 1011
bcs (blu) 0101 bcc (bgeu) 1101 tleu 0100 tgu 1100
bneg 0110 bpos 1110 tcs (tlu) 0101 tcc (tgeu) 1101
bvs 0111 bvc 1111 tneg 0110 tpos 1110
tvs 0111 tvc 1111
 Jump and Link Instructions The NOP Instruction
Assembler Syntax 
jmpl address , reg rd Assembler Syntax
nop
Instruction Formats
31:30 29:25 24:19 18:14 13 12:5 4:0 Instruction
31:3029:25
Format
24:22 21:0
10 rd 111000 rs1 0 unused (zero) rs2 00 00000 100 0000000000000000000000
10 rd 111000 rs1 1 siconst 13
 The UNIMP Instruction
 Return from Trap Instructions Assembler Syntax
Assembler Syntax unimp const 22
rett address
Instruction Format
Instruction Formats 31:3029:25
00 reserved
24:22
000
21:0
const22
31:30 29:25 24:19 18:14 13 12:5 4:0
10 00000 111001 rs1 0 unused (zero) rs2
10 00000 111001 rs1 1 siconst13
 The STBAR Instruction
Assembler Syntax
 Call and Link Instructions stbar
Assembler Syntax Instruction Format
call label 31:30
10
29:25 24:19
00000 101000
18:14
01111
13:0
unused (zero)
Instruction Format
31:30 29:0
01 disp30

2
 Read State Register Instructions  Synthetic Instructions
Assembler Syntax Synthetic instruction
bclr rs , rd
Implementation
andn rd , rs , rd
rd statereg , rd bclr rs , siconst 13 andn rs , siconst 13 , rd
Instruction
31:3029:25
Format
24:19 18:14 13:0
bset rs , rd
bset siconst 13 , rd
or
or
rd , rs , rd
rd , siconst 13 , rd
10 rd op3 rs1 unused (zero) btst rs 1, rs 2 andcc rs 1 , rs 2, %g0
btst rs , siconst 13 andcc rs , siconst 13 , %g0
btog rs , rd xor rd , rs , rd
Register Encodings btog rs , siconst 13 xor rs , siconst 13 , rd
state register op3 rs1 call address jmpl address , %g0
%y 101000 0 clr rd or %g0, %g0, rd
%asr1{%asr31 101000 1{31 clrb [address ] stb %g0, [address ]
%psr 101001 reserved clrh [address ] sth %g0, [address ]
%wim 101010 reserved clr [address ] st %g0, [address ]
%tbr 101011 reserved cmp rs 1, rs 2 subcc rs 1 , rs 2, %g0
cmp rs , siconst 13 subcc rs , siconst 13 , %g0
 Write State Register Instructions dec
dec
rd
siconst 13 , rd
sub
sub
rd , 1, rd
rd , siconst 13 , rd
Assembler Syntax deccc rd subcc rd , 1, rd
wr reg rs1 , reg rs2 , statereg deccc siconst 13 , rd subcc rd , siconst 13 , rd
wr reg rs1 , siconst 13, statereg inc rd add rd , 1, rd
inc siconst 13 , rd add rd , siconst 13 , rd
Instruction Formats inccc rd addcc rd , 1, rd
31:30 29:25 24:19 18:14 13 12:5 4:0 inccc siconst 13 , rd addcc rd , siconst 13 , rd
10 rd op3 rs1 0 unused (zero) rs2 jmp address jmpl address , %g0
op3
mov rs , rd or %g0, rs , rd
10 rd rs1 1 siconst13 mov siconst 13 , rd or %g0, siconst 13 , rd
mov statereg , rd rd statereg , rd
Register Encodings mov rs , statereg
mov siconst 13 , statereg
wr
wr
%g0, rs , statereg
%g0, siconst 13 , statereg
state register op3 rd
%y 110000 0 neg rs , rd sub %g0, rs , rd
neg rd sub %g0, rd , rd
%asr1{%asr31 110000 1{31 not rd xnor rd , %g0, rd
%psr 110001 reserved not rs , rd xnor rs , %g0, rd
%wim 110010 reserved restore restore %g0, %g0, %g0
%tbr 110011 reserved save save %g0, %g0, %g0
ret jmpl %i7+8, %g0
 FLUSH Instructions retl jmpl %o7+8, %g0
Assembler Syntax set iconst , rd or %g0, iconst , rd
|or |
ush address sethi %hi(iconst ), rd
Instruction Formats sethi
|or |
%hi(iconst ), rd
31:30 29:25 24:19 18:14 13 12:5 4:0
or rd , %lo(iconst ), rd
10 unused 111011 rs1 0 unused (zero) rs2 tst rs orcc %g0, rs , %g0
10 unused 111011 rs1 1 siconst13

 Assembler Directives
.align n
.ascii "string " [, "string "]*
.asciz "string " [, "string "]*
.byte 8-bitval [, 8-bitval ]*
.data
.global label [, label ]*
.half 16-bitval [, 16-bitval ]*
.include "lename "
.skip n
.text
.word 32-bitval [, 32-bitval ]*
 ISEM Traps
0 terminate program
1 putchar( %r8 )
2 blocking getchar( %r8 )
3 nonblocking getchar( %r8 )