3*8decoder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity DEG is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d0 : out STD_LOGIC; d1 : out STD_LOGIC; d2 : out STD_LOGIC; d3 : out STD_LOGIC; d4 : out STD_LOGIC; d5 : out STD_LOGIC; d6 : out STD_LOGIC; d7 : out STD_LOGIC); end DEG;

architecture Behavioral of DEG is

begin d0<=((not a) and (not b) and (not c)); d2<=((not a) and b and (not c)); d1<=((not a) and (not b) and c); d3<=((not a) and b and c); d4<=( a and (not b) and (not c)); d5<=(a and (not b) and c); d6<=( a and b and (not c)); d0<=( a and b and c);

end Behavioral;

RTL OUTPUT:

WAVEFORM

HALF SUBTRACTER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity VHG is Port ( a : in STD_LOGIC; b : in STD_LOGIC;

borrowhs : out STD_LOGIC; diffhs : out STD_LOGIC); end VHG;

architecture Behavioral of VHG is

begin

diffhs<=a xor b;

borrowhs<=((not a) and b); end Behavioral;