Thu Mar 03 14:35:32 2011 tb_testproc.

vhd 1 -------------------------------------------------------------------------------2 -- Company: 3 -- Engineer: 4 -5 -- Create Date: 14:19:40 03/03/2011 6 -- Design Name: 7 -- Module Name: M:/DSD_examples/processes/process/tb_testproc.vhd 8 -- Project Name: process 9 -- Target Device: 10 -- Tool versions: 11 -- Description: 12 -13 -- VHDL Test Bench Created by ISE for module: testproc 14 -15 -- Dependencies: 16 -17 -- Revision: 18 -- Revision 0.01 - File Created 19 -- Additional Comments: 20 -21 -- Notes: 22 -23 -------------------------------------------------------------------------------24 LIBRARY ieee; 25 USE ieee.std_logic_1164.ALL; 26 USE ieee.std_logic_unsigned.all; 27 USE ieee.numeric_std.ALL; 28 29 ENTITY tb_testproc IS 30 END tb_testproc; 31 32 ARCHITECTURE behavior OF tb_testproc IS 33 34 -- Component Declaration for the Unit Under Test (UUT) 35 36 COMPONENT testproc 37 PORT( 38 input : IN std_logic; 39 outvar : OUT std_logic; 40 outsig : OUT std_logic 41 ); 42 END COMPONENT; 43 44 45 --Inputs 46 signal input : std_logic := '0'; 47 48 --Outputs 49 signal outvar : std_logic; 50 signal outsig : std_logic; 51 -- Controls 52 signal done : boolean := false; 53 -- constants 54 constant in_period : time := 10 ns; 55 56 BEGIN 57 58 -- Instantiate the Unit Under Test (UUT) 59 uut: testproc PORT MAP ( 60 input => input, 61 outvar => outvar, 62 outsig => outsig 63 ); 64 65 -- generate a clock signal (input in this case)

Page 1

Thu Mar 03 14:35:32 2011 tb_testproc.vhd 66 input_process :process 67 begin 68 input <= '0'; 69 wait for in_period/2; 70 input <= '1'; 71 wait for in_period/2; 72 73 if done then 74 wait; -- stop the input_process loop 75 end if; 76 77 end process; 78 79 -- Stimulus process (no stimuli in this case, only simulation run time) 80 stim_proc: process 81 begin 82 wait for 100 ns; 83 done <= true; -- signal done to clock process 84 wait; -- wait forever 85 end process; 86 87 END; 88

Page 2

Thu Mar 03 14:34:37 2011 testproc.vhd 1 -- Company: CUAS 2 -- Author: 3 -- test process signal/variable behavior 4 library IEEE; 5 use IEEE.STD_LOGIC_1164.ALL; 6 use IEEE.STD_LOGIC_ARITH.ALL; 7 use IEEE.STD_LOGIC_UNSIGNED.ALL; 8 9 entity testproc is 10 Port ( input : in std_logic; -- single input line 11 outvar : out std_logic; --output from variable 12 outsig : out std_logic); --output from signal 13 end testproc; 14 15 architecture Behavioral of testproc is 16 signal temps : std_logic; --intermediate signal for process 17 begin 18 process (input) --process sensitive to input 19 variable tempv : std_logic; --intermediate variable for process 20 begin 21 tempv := not input; --invert using variable 22 outvar <= tempv; --output assignment 23 24 temps <= not input; --invert using signal 25 outsig <= temps; --output assignment 26 end process; 27 28 29 end Behavioral; 30

Page 1