Basic Analog Modelling of A Pattern Generator

Created by Zahrein b Yaacob

What is a Pattern generator

A pattern generator is an equipment to generate the digital electronic stimuli. A Digital electronic stimuli is a kind of electrical waveform varying between 2 conventional voltages that correspond 2 logic states which is (Logic 0 and Logic 1). The purpose of modelling the pattern generator is to verify the checkers in a fast time manner. Previously we use the Circuit Testbench that took longer period to stimulate. The checkers are the specs definition where we can validate the specs for the signal that is being generated. For example: We can check the Rise and Fall time of a waveform.
Pattern Generator output

Pattern Generator Specs/characteristics

Period cycle Low and High Voltages Duty cycle Slew Rate Filter Digital and Analog output

The block Diagram of a pattern generator.

Dig_clk

Digital waveform (1/0)

ana_clk

Analog waveform (1.05V/0V)

Pattern Generator TestBench

Creating TestBench and Verilog AMS Model

module tb_test_ver(); //testbench module name wire pina, pinb; // declaring wire input pat_gen i_pat_gen (.a(pina),.b(pinb)); // put the variable a into pina measure_riset_fallt check1 (.drive_en(1'b1),.pad(pinb)); initial $vcdpluson; //log on vpd file for dve initial #(50000) $finish; //set to run for 50,000ps

endmodule
//.probe V(*)

Pat_gen verilog file

module pat_gen (a,b); output a,b; wire a; dig_clk clk0 (.clk(a)); ana_clk clk_ana (.clkin(a),.clkout(b)); endmodule

Dig_clk verilog file

module dig_clk ( clk ); output clk; logic clk; initial begin clk = 0; forever #1000 clk = ~clk; //invert clk for every 1000ps end

endmodule

Ana_clk
module ana_clk ( clkin,clkout );

input clkin; output clkout; parameter amplitude =1.05, dly=0, ttime =100p;

analog begin //V(clkout)<+ amplitude*V(clkin) ; V(clkout)<+transition(amplitude*V(clkin),dly,ttime); $bound_step(100f); //max step

end

endmodule

Waveform Simulations

Fr Files- must include all the verilog file path.

Path..pat_gen.v Path .dig_clk.v Path..ana_clk.v Path(my module checkers)z_checkers.va amsexec $AMSTESTS/tb_test_ver.vams -unit scratch_lib -sgn -dve allsigs command to execute

Checkers
Rise Time & Fall Time