S1 S2

Vs 12V
12V_25W

fig 2.1

And Gate IC Internal ckt diagram with pin conf

fig 2.2

fig 2.3

FIG 2.4
Fig 2.5 a

Not shown

Fig 2.5 b

Vs 12V

Fig 2.6

Fig 2.7
Not shown

Fig 2.8

S1

S2

Vs 12V 12V_25W

Fig 2.9

D1
A
D2
B

Fig 2.10

Fig 2.11

Fig 2.12

OR Gate IC
Fig 2.13

Not shown here

Fig 2.14

Fig 2.15

Fig 2.16

XOR IC

Fig 2.17

Fig 2.18
Timming diagram

Fig 2.19 (a)

Not Shown

Fig 2.19 (b)

1 2 1 2

1 2 1 2 1 2

Fig 2.20

VCC

Rc
Out

RB
IN

Fig 2.21
VCC

Rc
Out = 0V

IN = Vcc

Fig 2.22
 VCC

Rc
Out = Vcc

IN = GND

Fig 2.23

NOT Gate IC

1 2
A

Fig 2.24

Timming Diagram

Fig 2.25
 1
A 3
2
B

Fig 2.26

Timming Diagram

Fig 2.27

Fig 2.28

Exercise

A NAND gate is equivalent to an inversion followed by an OR

A NOR gate is equivalent to an inversion followed by an AND