a1 0 0

a0 0 0

b1 0 0

b0 0 1

p3 0 0

p2 0 0

p1 0 0

p0 0 0

Chng 6. B

nh

1
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5.1. Vai tr c a b

nh

iv ih

th ng my tnh

5.1. Vai tr c a b

nh

iv ih

th ng my tnh

B nh chng trnh: cho php lu tr , l y ra, thay i chng trnh B nh d li u: lu tr d li u trong qu trnh chng trnh tnh ho c k t qu ch y chng trnh. B nh trong (chnh) v b nh ngoi (ngo i vi) B nh trong : thng tin c lu tr v l y ra v i t c r t nhanh B nh ngoi: th ng c dung l ng r t l n hn so v i b nh trong nhng ch m hn so v i b nh trong. B nh ch a cc bit thng tin. T : nhm cc bit bi u di n cho m t th c th thng tin. di t : c th t 4 n 32 bit ho c nhi u hn. nh : t p cc ph n t c th lu tr m t t . Ch ng h n: nh ch a t 8 bit c th g m 8 trig. Dung l ng b nh : th ng c bi u di n theo b i c a 210 = 1024 (K) 211 = 2048 = 2K, 216 = 65536 = 64K
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My tnh

n v s h c

n v i u khi n

B nh trong (bn d n)

n v x l trung tm (CPU)

B nh ngoi (bng, a)

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Cc thao tc i v i b nh 1. 2. 3. 4. 5. Ch n a ch trong b nh ang c truy nh p c ho c ghi L a ch n thao tc c ho c ghi c n ph i th c hi n Cung c p d li u vo c n ph i lu tr trong qu trnh ghi Duy tr d li u ra l y t b nh trong qu trnh c Kch ho t (ho c khng kch ho t) b nh b nh s (ho c khng) c p ng i v i a ch a vo v l nh c/ghi

5.2. T

ch c b
a ch

nh
D7 0 1 0 0 1 1 0 1 0 1 D6 1 0 1 0 1 0 1 1 0 0 D5 1 0 0 1 1 1 1 1 0 0 D4 D3 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 0 1 D2 0 0 1 1 0 1 0 1 0 1 D1 0 0 1 0 0 0 1 1 1 0 D0 0 1 1 0 0 1 1 0 1 1

00 01 02 03 04 05 06 07 08 09

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Chip nh 8 t
Bus s li u 8 bit 2 chi u

x 4 bit Vo

I0

I1

I2

I3 CS

CPU

B nh a ch

A0 A1 A2 O0

8t x 4 bit WE O1 O2 O3

Chip Select Write Enable

ghi

Bus a ch 16 bit 1chi u Tn hi u i u khi n

Ra

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56

I1

Vo

I0

Gi i m T T a ch A0 A1 T T 0 1 CS 2 3
Io I1 I2 I3 CS WE A2 O4 I4 A0 A1 I5 I6 I7 CS WE

CS WE

WE a ch

A0 A1 A2 Oo

8 t x 4 bit Chip 1 O1

8 t x 4 bit Chip 2 O5

O2 O3

O6 O7

O1

Ra

M c song song 2 chip nh 8 t O0

225

4 bit t o thnh chip nh 8 t

8 bit

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226

M c song song chip nh tng dung l ng b nh CS (A3) WE Bit line CS

Io A0

I1

I2

I3 CS WE

Io A0 A1 A2 Oo

I1

I2

I3 CS WE

a ch

A1 A2 Oo

8 t x 4 bit Chip 1 O1

8 t x 4 bit Chip 2 O1

Read / Write

O2 O3

O2 O3

I/O Bit vo, ra chung m t ng Bus chung

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57

x
q1q2q3

0 000 000 001 001 010 010 011 011

1 100 100 101 101 110 110 111 111

x
q1q2q3

0 000 000 001 010

1 100 100 100 100

000 001 010 011 100 101 110 111

000 001 010 100

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