ee CONTENTS ee Preface as 1 MOS Transistor Models 1 Inrodestion 1 HI MOSFET ond Juncon FET 2 Ved JRE 2 Lia Most 2 3 MOST and pMOST ’ 112 Capaciances and MOST Taresbold Volages 3 TL MOS Capsciasce 5 122 Juseten Capactance 6 123. MOST and JPET 7 124 MOST Threshold Yolage 9 1-2-5 _Baancenent and Depiction MOST 2 ‘OSD iar eps nd Sion Reon 4 11 Lage vos, Stall vps, and Ze0 vas rn 132. Lage oe: Lage vss and Za as 6 42. Large wos, Small pps and Largs Yas ” 1-4 MOST Curen-Voiage Characeriics a TL Linear Region n 142 Linear Region: Fine-Osler Motel 8 1463 MOST ia Sauatoe: First-Order Mote 8 [ot Parameters A and » 13 Pls of fog verws vas and vas 2 14.5 _ifecive Charme Length snd Width B (LS Small-Sigual Model in Sarason 2 1 Transeonductnc fe 2552 Dull Tanscondusasce snp 1:53 Outpt Resistance 7, ‘Weak Inversion snd Velesity Saturation 61 MOST in Wisk Inversion 1452 Transconducaoe-Ouret Ratio 163 Trasion Weak-Steng lnverion 1h MOST in Yeocky Suuration ‘Examples of Smll-Signal Analysis xanple of Tensconducance Amplifer "xanpie of Voltage Amplier with Active Load Exanple of 2 MOST Disde Bxample of Source Pollewer ‘Example of MOST #8 a Swish with Resistive Load 176 Bump wih MOST oe Sei ih Cape Land apactncos "MOST: Oxide Capacitance Cou 182 MOST funtion Cupuciences’ 8:3 MUSI Juncion Leaage Curent and Capscances 184 Interconnect Capsciances 18S Bowling Pad Capaciance 1-8-6 Package Pin Capecitinoe [68:7 Protetion Network Capscitance 1683 Tol Copaciunce Configurations Higher-Order Medels Sst VTO-KP-GAMMA-LAMBDA or TOX-PHLNSUB-NSS? Paraie Rssances Mobility Deprattion Duet Longtulina Elet Fed “Mobility Depradtion Due to Transverse Elects Field (Chanaal With Facer DELTA Satie Feetack Fert Parmeter BTA (Ont of Short-Channel Effects Punchthrough and Substate Cures Design Example Jneion FETE I-I1-L TFET Piacolf Voltage 112 REP DC Model LES JPET: DC Model in Linets Region -LE4 JRET DC Model: Onset of Sturation LL JREP DC Model in Sion LS. Model for Wide-Channel JFETS VLLT JRET DC Model in Saturation: Subtresold Region -LG8 JFET Sml-Signal Models TIL JPET Example: MESFET 1-10 SFE Design Example Noise Soares ia FET 1-121 Thana ot Joon Noise 1122 Shar Nose 15123. 1/7 Noise or Fcker Noise Bipolar Transistor Models a a4 as CONTENTS xi 142-4 Otter Nolee Sources " 1125 Taal Noise u 1112.6 FET Noise Madels 6 127 1/7 Nobse in SPICE u 112-8 Equivalent Input Noise Curent 112.9 Gute Leshige Noize © Summary 6 Brercses 6 Append It: Notion of Symbols 50 References o Bhpolse Transistor Operation Bil Stuctire 2-2 Depletion Layers 213 Bue Doping 21-4 Forward Basing 213 Bue Transit Time ‘The Tensistr Beta (8) 22:1 Bean Caused by Ietion inthe Eine: pre 222 Ben Caused by Recombinton inthe 3ase Ben 22:3 Baa Caused by Recordin i the JB Space Charge Layer 224 AC Beta fac “The lybier Small Signal Madel 2341 Transcondicanee fm 232 put Resistance re 23.3 Ou Resismce ro 284 Volige Gain of Small-Sipal Gain tae 23:3. Junction Capaciances 236 Diffron Capacitance Co 23 Commoner Conigratin with Curent Dive 238 Common-Emiter Configuration wih Nags Drive 239 CommonrCollctr end Common Base Conigulioas ‘The Ohwnke Resistance: 21 The Base Resitance 242 Bernie Bae Rertance 2-43 Inti Base Resstnce 24-4 ‘The Collector Ressanoas 245 The Biter Reisanoe High-njection and Other Second-Order iets 251 Highljeton Bet inthe Base 25-2 Highinjection Model of Bets 25.3 ate Resistance Beis 254 Gide! Base 25:3 Collector Curent Spreaiog 25.6 High -jecion Bets inthe Collector 12 25 Bipolar Tansisor for VLST Lateral gop Transtar 26-1 Sabstate pep Trasorsil CONTENTS. Lace pp Tensions Base Wiat, Esty Voge, sod Punchough Base Reistanoe and Emitter Crowding Applies with paps Input Nie Sees Elen inp NeeSouees Naw gue Onin fe Optinan Onin fe 28 Dein Beane 29° Oar Conor 2 Bate Diftxon Reson 202 Ofer Restor 253. Tempers Concent 204 Vatage Corer 253° Tregesy Dependence 256 Alte Reatve Acuney 297, Reskon ina GMOS Posse 298 This Fim Reston 239. Caper 20:10 tnd 2110 Compares buen MOST: an Bier Tessas 2IOt nat Caren 2102 be Satin Voge 2.103 Tronics Core Rao 2104 sgn Pamiog 15 Canes Range 210 Masini Resuney of Opcaee 210-7 Noise st Susman Bec dopac 24 Relea 3 Feedback and Sensitivity in Analog Integrated Circuits 31 Feedback Theory SAL Basic Feedback Co 31-2 _Reedback Configurations and Csifstios 3-2 nase of Featack Amplifr Cacuks 32:1 Anais When te Feedback Network is One of he Fear Basic Configurations i Fig. 3-7 322 Blackman’ Impodance Relation 32.3 The Asymptis Gai Relaon 33 Stability Consideration in Linear Feedback Sytens 3541 "lest of Feeitack onthe Sysem Natural Frecuenies ‘Te Use of Bde Pas in Stay Analysis 130 131 132 153 153 153, Iss. 156 137 189 198 200 202 a2 M4 Sexsiivity, Coorpooent Maching and Ved S4e1 - Cocpponent Matching 5.42 Sentty Problem to Precision Analog Cet S463 Ved Considerations in Analog Inepratd Ccts Suny Barco Agponi 3l: Approximate Caleulton fra Two-Pole System when the Poles tee Rel and Widely Seprted ‘Appendin 2: ExattCaleuliion ofthe Bode Daren for Two-Pole Sytem References 4 Elementary Transistor Stages Intoetinn 4 “8 as 46 ‘MOST Single‘Teasstor Amplifying Stages ‘1 Bislng 12 Low Requney Gain 4:14 Full Creu Pestomance a High Fregutacies 415 Unity Frequency and Gaie-Bardwih Product 416 | Noite Performance ‘Bgoar Single Trasisor Ampying Sages 421 Biting 422 Gain for Voluge Dive and Curent Drie 423 Frequency Pesformance 424 Gai-Bandvith Product, 425 Input Impedance Source and Emits Flowers 431 Source Folower 432 Ente Fllovers 453 _ Noise Perfomance (Casco Traitor, 441 MOST Caicodes $42 Bipolar Tascistor Cascodes 443 _ Noise Pecfonnunce (CMOS teverer Sages 451 DC Atalyals of CHOS lovers 43:2 Low Frequeney Gala Bandwidth Current Capit and Siew Rate 43:3. Design Prcedate 46 Other MOST lnvenece 45:7 Bipolar Tansstor inverter Stages ‘45:8 Nole Perfomance Cacole Sages 1 Caseode Coniguratons Bandwidth of Cascode with Low Re Cecio with Active Load Nase Performance igh Voltage Cascode 219 ni 2 25 a 2m 238 Bi 38 3 36 382 353