Eisagogi

:
: , .
Tanenbaum, Vrije Universiteit, Amsterdam.
Computer Architecture and Engineering, K. Asanovic, CS1/2-52,
University of Berkeley.
, . ,
.
, .
,
, . , .
: .. , ,
.
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

, , ,

,
Pentium 4

,
.
19/10/08
3
CS252-s06, Lec 01-intro
, ,

(1)

assembly

( )

.
() .
(2)

Assembly
Assembler, Linker Firmware

. . . I/O
cslab@ntua 2007-2008

temp=v[k];
v[k]=v[k+1];
v[k+1]=temp;
load$15,0($2)
load$16,4($2)
store$16,0($2)
store$15,4($2)

Assembly
Assembly,
ISA
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
,
Control Signal
Specification
ALUOP[0:3] <= InstReg[9:11] & MASK
Register Transfer Notation (RTN)

7
(1)
:
(Instruction Set Architecture, ISA),

( Assembly
).
( )

( ) .
() ,
( ), ,
,
, /,
.

.
8
9
10
(2)
(Microarchitecture),
,
.
,
( ),
( )
.
.

(Instruction Level Parallelism, ILP),

.
11
12
(3)
(System Design)

() , ,
,
:
1. ( , )
2. , , , .
3. - (GPUs, DMAs, NICs)
4. .
13

1. Top Down
> > >

2. Bottom Up
> > >

* (Hardware/Software Co-design)
* (Backward Compatibility)
14
,
().
= , , ,
,
,
= , ,

= ,
() ,
..
15
(1)
Time = I x CPI x Clock Cycle Time
- I: Instrumentation ( ,
)
- CPI: Cycles Per Instruction (, o)
- Clock Cycle Time: ( )
, CPI Clock Cycle Time (
)
Clock Cycles = CPIi x i
i:
(CPIi) (i) .
16
(2)
FLOPs: Floating Point Operations per Second
MIPs: Million Instructions per Second
MIPs = / 106 /CPI X 106
1
( ) :
1GHz, 1 GFLOP
1 , 1000MIPs
4 x freq FLOPS < {single Core 2 @ 2.93GHz} < 8 x freq FLOPs

, FPADD, FPMUL, FPDIV ( ).
12 GFLOPs/cpu
17
(3)
SPEC Benchmark ()
www.spec.org
i execution ratio (ER)
ERi=( 300 MHz UltraSun 5_10 /
)* 100
Execution Ratios n

______
SpecRatio = (ERi) i=1,2,..,n
- SPEC CPU2006: 12 integer 17 floating point
- SPECThroughput, SPECJava...
18
TOP 500, 13/06/08
19
()
* Patterson & Hennessy, Computer Organization and Design
, .
'' .. MIPS. .
* Bryant, O'Hallaron, Computer Systems: A Programmer's

Perspective
. '' .. 32.
. .
* Tanenbaum, Structured Computer Organization

, , .
. .. .
.
*Hamacher et.al., Computer Organization

*Stallings, Computer Organization and Architecture.
. .
20
()
* Compus, httlp://compus.uom.gr
, , , .
* PdP Lab, http://www.it.uom.gr/teaching

, ,
.
Compus.
* Wikipedia
computer architecture .
* Google..
21
1-2
3-5
6-8
9
10
11-12
13
, ,

..,
(ssembly)

1,2,3
4
5
6
7
8
-
22

.
(. , ).
'
: ', 4
5 - 6,7 8.
1,2 3, .
, .
MIC-1.
Intel gcc, gdb / ddd (Linux).
/ (+20%).
23

, , ,

,
Pentium 4

: , , (1945)
(1950)
(1960)
(1970)
(1985)
: , , (2000)

(VLSI)

(1)

.
(2)

.

(1642 1945)

(1945 1955)

-Transistors (1955 1965)

(1965 1980)

-VLSI (1980 ?)
19/10/08
EDSAC, University of Cambridge, UK, 1949

29
Von Neumann.
bit-level .
.
PDP-8.

().
-.
IBM 360: .
.
.

- (
Intel).
( PC)
().
(Miscrosoft MSDOS)
(3rd parties).
VLSI: , .

-
.
: -

.
Moore (1)
(K) (LSI, VLSI).

Moore 60%
transistors chip.
bits.
Moore (2)
:
2X 1.5 .
~1000X 10.
:
DRAM : > 2x 1.5 .
~1000X 10.
bit: 25% .
:
: > 2X 1.5 .
bit: 60% .
200X 10.
35
..
Sensor Nets TIFFQuickTime
(Uncompressed)
decompressor
are needed
toand
seeathis
picture.
Cameras
Games
QuickTime and a
Set-top
TIFF
(Uncompressed) decompressor
are needed to see this picture.
boxes
Media
Players
Laptops
Servers
QuickTime and a
TIFF (Uncompressed) decompressor
QuickTime and a
TIFF (Uncompressed) decompressor
Routers
Smart
phones
Automobiles
19/10/08
Robots
Supercomputers
36
,
.

- Pentium 4 Intel (-32)
- UltraSPARC III Sun Microsystems
- 8051 chip Intel,
- PS,
- ARM,
- PIC,
?
:
.

, , ,

,
Pentium 4

(PC)
.
''
(, )
CPU I/O
CPU
Address Content
00..0
01100..0
MAR, MDR
PC, IR
FF..F
0100..0
Memory
CPU
( ) CPU
= , ALU, .
(Program Counter, PC)

(Instruction Register, IR)
(Memory Address Register,
MAR)
(Memory Data Register, MDR)
(Accumulator, AC) , , C...
(Stack Pointer, SP)
Index, Base, Offset Registers
(Status Register, SR)
-
A.

B.

C.

D.
,
() CPU
E. ()
CPU
F.
(1)
...
( Java).
(2)
( Java).

. . -ROM.
.

( ).
.
/ ( ).
( -ROM )
T CPU

(1-address)
.
- .
( ).
(0-address)
( )
(Push, Pop).
,
. JVM.
(0,1,2-address)
. ( ) .
( RISC,
CISC)
AC

AC
int x, y, z;
x = y + z;
load 0xA2
add 0xA4
store 0xA0
Assembly
// AC := AC + mem(0xA4)
0100 1010 0010

0110 1010 0100
0101 1010 0000
IR := MDR(PC); PC := PC + len(instr);
Decode (Opcode(IR);
MAR := Operand(IR);AC := MDR(MAR);
Stack

Stack
int x, y, z;
x = y + z;
load 0xA2
load 0xA4
add
store 0xA0

push 0xA2
push 0xA4
Assembly
// pop, pop, add, push
pop 0xA0
0100 1010 0010

0100 1010 0100
0110
0101 1010 000
Regs

Regs
int x, y, z;
x = y + z;

``
load A, 0xA2
load B, 0xA4
add C, A, B
store C, 0xA0
Assembly
load A, 0xA2
add C, A, OxA4
store C, 0xA0
0100 0000 1010 0010

0100 0001 1010 0100
0110 0010 0000 0001
0101 0000 1010 0000
add C, 0xA2, 0xA4

store C, 0xA0
add 0xA0, 0xA2,0xA4
;
, ;
(/ /)
,
,
( PC)

( )
/'o
/
:
Top 10 Intel X86 Instructions
load
22%
conditional branch
20%
compare
16%
store
12%
add
8%
and
6%
sub
5%
move register-register
4%
call
1%
10
return
1%
Total
96%
: .
57
RISC CISC
(VAX).
(200-300 ).
- .
Complex Instruction Set Computer (CISC)
.
. ,
' . ..

.
- ''
.
Reduced Instruction Set Computer (RISC)
.. .
(MIPS, SPARC, PowerPC, ..) ? RISC
(Pentium, ..) ? CISC RISC (
..).

' (
).
CPU
( , ILP).
(
).
,
Load, Store .
( register file).

(Data Level Parallelism, DLP):
, ALU,
, (32/64 bits, GPU).
(Instruction Level Parallelism, ILP):
(
, ).
(Task/Thread Level Parallelism, Multithreading):
().
(Functional Parallelism):
( GPU, DMA, I/O ..)
/ (Multiprocessors, Multicomputers):

.
(ILP)
CPU,
- .
, PC

A
10
C
D
E
(ILP)
Pipelining (, )
()
() .
(ILP)
(Superscalar) (1)

( Pentium, ).
(ILP)
(Superscalar) (2)
,
(Pentim II).
(ILP)
(Superscalar) (3)
10
C
D1
D2
D3
D4
D5
E
96 bit.
Bytes (1)
(a) Big endian (b) Little endian
Bytes (2)
(a) big endian.

(b) little endian.
(c) big endian little endian.
(d) bytes (c).
(Cache) (1)
() cache
CPU .
(Cache) (2)
() ,
cache (L1/2/3)
,
(, ).

.
:
: ,
.
:
: ,

: .
Cache
L1 > K L2 > L3 > .
L1 < L2 < L3 < .
L1 < L2 < L3 < .
Cache < 1%
:
* Cache (
).
* Cache , .
* Cache .
L1 Instruction/Data on chip
L2 on chip package
L3 on board
*
Virtual memory
*
/
( ) .
( *).
(1)
.
(2)

(Data Bus): MDR,IR, AC (A, B, C, ...)
(Address Bus): MAR, PC, SP, Index,, Base
(Control Bus): ..
masters slaves .
(1)
.
(2)
(1)
(a) .
(b) .
(2)
/' (/O)
/.
I/O ''
(memory mapped I/O)
/.
8259A .
(1)
EPROM, RAM, PIO 64 KB.

(2)
.

, , ,

,
Pentium 4
Intel (1)
CPU Intel. MHZ,

1 MHZ = 1 . /sec.
Intel (2)
Moore CPU chips Intel.
Pentium 4 (1)
Pentium 4t.
Pentium 4 (2)
chip Pentium 4 Intel, 2003.

Pentium 4

,

.
PC
1. Pentium 4 socket
2. 875P Support chip
3. Memory sockets
4. AGP connector
5. Disk interface
6. Gigabit Ethernet
7. Five PCI slots
8. USB 2.0 ports
9. Cooling technology
10. BIOS

(motherboard) : Intel D875PBZ board.
Pentium 4.
Pentium 4
Block .
PCI
PCI .
PCI
,
,
.
Universal Serial Bus (USB)
USB 1 ms.
(Parallel I/O)
8255A PIO.

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:

Assembler, Linker Firmware

ALUOP[0:3] <= InstReg[9:11] & MASK

Register Transfer Notation (RTN)

4 x freq FLOPS < {single Core 2 @ 2.93GHz} < 8 x freq FLOPs

TOP 500, 13/06/08

* Bryant, O'Hallaron, Computer Systems: A Programmer's

* Tanenbaum, Structured Computer Organization

*Hamacher et.al., Computer Organization

* PdP Lab, http://www.it.uom.gr/teaching

EDSAC, University of Cambridge, UK, 1949

(K) (LSI, VLSI).

CS252-s06, Lec 01-intro

(Program Counter, PC)

0100 1010 0010

0100 1010 0010

0100 0000 1010 0010

add C, 0xA2, 0xA4

add 0xA0, 0xA2,0xA4

(a) Big endian (b) Little endian

(a) big endian.

EPROM, RAM, PIO 64 KB.

CPU Intel. MHZ,

Moore CPU chips Intel.

chip Pentium 4 Intel, 2003.

Universal Serial Bus (USB)

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