PERIPHERAL INTERFACE CONTROLLER

Architectural Features

• Harvard architecture
• Long word instructions
• Single word instructions
• Single cycle instructions
• Instruction pipelining
• Reduced instruction set
• Register File architecture
• Orthogonal instructions
Harvard Architecture

Program
Data memory
memory CPU
8 14

•Has program memory and data memory as separate memories.

•Both are accessed from separate buses.
•These separate buses allows instruction pipelining.
Data memory

• Partitioned into multiple banks. Base-line Mid- High-end

range
• Each bank contains general
No. of
purpose registers and special
banks 2 4 14
function registers.
(max)
• Each bank extends upto 7Fh.
(128 bytes).
• Some frequently used SFRs in
one bank may be mirrored in
another bank for code reduction
and easy access.
Program memory
Reset vector 000h Base- Mid- High-
line range end
Address 8K 8K 2MB
(max)
Program 13-bit 13-bit 21-bit
Interrupt counter
vector 0004h

0005h

On-chip
memory
Instruction flow/pipelining
TCY0 TCY1 TCY2 TCY3

• Instruction cycle consists of 4 Fetch 1 Execute 1

Q cycles. Fetch 2 Execute 2
• Fetch takes one instruction Fetch3 Execute 3
cycle while decode and execute
takes another instruction cycle.
• Due to pipelining, each
instruction effectively executes
in one cycle.