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  • Questions in VHDL Lab

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    harrisraj
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    This document outlines questions for a VHDL lab assignment involving digital circuit design. The questions cover: 1) Designing a decade counter and mod-5 counter using structural and behavioral modeling respectively. 2) Designing iterative and parallel comparators using structural and behavioral modeling. 3) Implementing MEALY and MOORE finite state machines to detect input/output sequences. 4) Designing a BCD adder from 0-99. 5) Designing 1's complement adders and subtractors.

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    VHDL lab

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    This document outlines questions for a VHDL lab assignment involving digital circuit design. The questions cover: 1) Designing a decade counter and mod-5 counter using structural and behavioral modeling respectively. 2) Designing iterative and parallel comparators using structural and behavioral modeling. 3) Implementing MEALY and MOORE finite state machines to detect input/output sequences. 4) Designing a BCD adder from 0-99. 5) Designing 1's complement adders and subtractors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    22 views1 page

    Questions in VHDL Lab

    Uploaded by

    harrisraj
    This document outlines questions for a VHDL lab assignment involving digital circuit design. The questions cover: 1) Designing a decade counter and mod-5 counter using structural and behavioral modeling respectively. 2) Designing iterative and parallel comparators using structural and behavioral modeling. 3) Implementing MEALY and MOORE finite state machines to detect input/output sequences. 4) Designing a BCD adder from 0-99. 5) Designing 1's complement adders and subtractors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
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    Questions in VHDL lab

    1) Ripple counter design a) Decade counter using structural modelling. b) Mod 5 using behavioural modelling. 2) Comparator a) Iterative comparator using structural modelling. b) Parallel comparator behavioural modelling. 3) Finite state machine a) Implement MEALY FSM sequence detector for detecting 1 0 0 in one input sequence using behavioural modelling. b) Implement a MODE FSM for tracking 1 1 1 in one output sequence. NOTE: Assume overlapping in one input sequence will be present. 4) Bcd adder in the range 0-99 5) 1s complement adder and subtractor.

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