AVR

The 5th Lecture

( yoo@netplug.co.kr)

INDEX
1

(Interrupt)

AT
ATmega128
128

ATmega128

: AVR C

ATmega128
g
:

(I t
(Interrupt)
t)

(S/W)
y

y (CPU)

y ) /

(H/W)
y ( )
y (CPU)
y )

(I t
(Interrupt)
t)
Application
(System) Library

User Level

System Call Hacking

Software Interrupt

Kernel Level
System
y
Call

Virtual File System

General File System

Device File System

Buffer Cache
Block Device Driver

Network File System

TCP/IP Protocol Stack

Character Device Driver

Network Device Driver

Device Interface
Block Device

Character Device

Network Device

(I t
(Interrupt)
t)

Application

(System) Library

Software
Interrupt

System Call

sys_open()
int main()
{

open()
{

Interrupt Vector (5)

open();

swi 0x900005;

Interrupt Vector (4)

Interrupt Vector (3)

}
Interrupt Vector (2)
Interrupt Vector (1)
Interrupt Vector Table

fd = open();
sd = socket();

User Level

Kernel Level

(I t
(Interrupt)
t)

write()

copy_from_user()

Device Driver

read()

copy_to_user()

wake_up()

ATmega128

Sleep

Network Device (H/W)

(I t
(Interrupt)
t)

3 Polling
P lli vs Interrupt
I t
t?
3 Interrupt on (H/W) BUS ?

AT
ATmega128
128

ATmega128 Interrupt Vector Table

AVR Assembly Code

AT
ATmega128
128

AT
ATmega128
128

SREG
: Status Register

Register

SREG

AVR Core Status Register ALU

sei();
// <avr/interrupt.h>
// #define sei()
__asm__ __volatile__ ("sei" ::)

MCU ALU
Bit7. I (Global Interrupt Enable)
: -> !!!
1

SREG |= 1<<SREG_I;

AT
ATmega128
128

EIMSK
: External Interrupt Mask Register

Register

Bit 7:0

1 (= Masking)

EIMSK = (1<<INT4);

AT
ATmega128
128

EICRA
: External Interrupt Control Register A

Register

EICRA

(Trigger Signal)

EICRA = (0<<ISC21) | (0<<ISC20);

ISCn1

ISCn0

Trigger Signal

The low level of INTn

(reserved)

The falling edge of INTn

The rising edge of INTn

// INT2 Low

AT
ATmega128
128

X Falling edge

Z Rising edge
Signal

Y Low level

AT
ATmega128
128

EICRB
: External Interrupt Control Register B

Register

EICRB

(Trigger Signal)

EICRB = (0<<ISC41) | (0<<ISC40);

ISCn1

ISCn0

Trigger Signal

The low level of INTn

(reserved)

The falling edge of INTn

The rising edge of INTn

// INT4 Low

AT
ATmega128
128

Interrupt
main program

main program
Interrupt

Interrupt
register bit

Interrupt
trigger

SREG,
EIMSK
1

EICRA/B
SREG

main prog.
PC

EIMSK

EICRB

Interrupt
vector

PC

: AVR C
int main()
ioport init()
ioport_init()

cli();

// &

ioport_init();
}
timer_init();

&

sei();

timer_init()
{
// / &

for(;;)

}
}

AT
ATmega128
128 :