Microprocessor

Micro + Processor = Processing at micro level

P
Prof. S A Waheed Raye

Manufacture of P

LSI Technique

VLSI Technique

BLOCK DIAGRAM FOR MICROPROCESSOR

Output devices

microprocessor

Memory

Input devices

Simple representation of microprocessor

ALU
REGISTER CU

Block diagram representing ALU

Main storage

Storage registers

comparator

Adder

Accumulator

REGISTERS OF 8085 MICROPROCESSOR

Sign Zero Carry Auxiliary Carry Parity

S
Accumulator A (8) B (8) D (8) H (8) Stack pointer Program counter

AC

CY
GEN REGISTERS + 16B MEMORY ADDRESS DATA PT

Flag Register (8) C (8) E (8) L (8) (SP) ( ) (PC) ( )

ACCUMULATER
A PART OF ALU

A
ALL ARTHMATIC AND LOGIC OPRATION RESULT AFTER OPERATION ARE STORED HERE

FLAG REGISTER
Sign Zero Carry Auxiliary Carry Parity AC P CY S Z

PART OF ALU

STATUS OF FLAG IS DATA IN REGISTERS , ACCUMULATER DEPENDS ON OPERATION

PROGRAM COUNTER
Program counter (PC) ( 16 )

SEQUENCES THE PROGRAM POINTS TO NEXT MEMORY ADDRESS

AFTER EXECUTION OF ONE ADDRESS

STACK POINTER
Stack pointer (SP) ( 16 )

POINTS TO THE STACKS OF MEMORY FIRST IN LAST OUT INSTRUCTIONS

CONTROL UNIT
CONTROL THE OPERATION OF ENTIRE MICROPROCESSOR TIMING AND CONTROL SIGNAL ARE GENERATED HERE

TRANSFERS DATA BETWEEN MEMORY AND INPUT/OUTPUT

CLK

TIMING AND CONTROL UNIT

WR ALE S0 S1 I0 / M HLDA

CLK out

RD

RESET out

READY

HOLD RESET IN

PIN DIAGRAM OF 8085

REST OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR
IO / M

VCC +5V HOLD HLDA CLK OUT RESET IN READY S1

INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GRD

CRYSTAL

RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8

Machine Cycle
TIME
Execute Cycle (EC)

Fetch cycle (FC)

INSTRUCTION CYCLE (IC)

VARIOUS CYCLES IN MICRO PROCESSOR

INTA
INTR
RST5.5 RST7.5 TRAP RST6.5

SID

SOD

Interrupt Control
8 bits internal data bus Instruction Register

Serial I/O control

Accumulator (8)

Temporary Register Flag (5) Flip - Flop

multiplexer

ALU

Instruction Decoder And Machine Cycle Encoding

W 8 Z 8 B 8 C 8 D 8 E 8 H 8 L 8 STACK POINTER 16 PROGRAM CUNT 16 INC/Dec add Lac 16

Address buffer

Data/ Address buffer

CLK

TIMING AND CONTROL UNIT

CLK out RD READY WR
ALE S0 S1

Reset

A15 A8 Address bus

AD7 AD0 Address/Data Buffer

RESET out HLDA I0 / M HOLD RESET IN

Registers array

Register select

COMMANDS OF MICROPROCESSOR
TO PERFOM A TASK MICROPROCESSOR NEED PROGRAM

PROGRAM NEEDS COMMANDS

COMMANDS
RESIDE AND ARE DESIGNED
IN P

COMMANDS

=
INSTRUCTION

INSTRUCTION = TASK TO BE PERFORMED + DATA

TASK TO BE PERFORMED IS OPERATIONAL CODE

OPCODE

OPCODE IS BUILT INSIDE P

TOTAL GROUP OF INSTRUCTION IS CALLED INSTRUCTION SET

CAPABILITY OF p DEPENDS ON STRENGTH OF INSTRUCTION SET P POSSES

PROGRAMS ARE DEVELOPED IN

ASSEMBLY OR MACHINE LANGUAGE

LENGTH OF INSTRUCTION
OF 8085 VARY FROM

1 BYTE TO 3 BYTE

Ist BYTE
IS ALWAYS

OPCODE

II nd & III rd

Byte IS EITHER AN OPERAND (DATA ) OR ADDRESS

FIVE TYPE OF INSTRUCTIONS

1. DATA TRANSFER GROUP 2. ARTHMATIC GROUP 3. BRANCH GROUP 4. LOGICAL GROUP 5. STACK INPUT/OUTPUT MACHINE CONTROLL

DATA TRANSFER GROUP

MOV R2, R1 MOV R, M M={HL} MOV M, R1

MVI R1, DATA MVI M , DATA LXI RP DATA(2+3BYTE) LDA ADDR STA ADDR

DATA TRANSFER GROUP

LHLD ADDR L< H < +1
SHLD ADDR ADDR< L ADDR+1< H LDAX RP A<RP STAX RP RP<A

ARITHMATIC GROUP
ADD R = [(A)+(R)]
ADD M ADDI DATA ADC R ADC M ACI DATA DAD Rp [A] SUB R SUB M SUI DATA [(A)-(R)]

ARITHMATIC GROUP
INC R INC M DCR R DCR M INX Rp DCX R:p DCX Rp DAA

BCD

BRANCHING GROUP
CONDITIONAL NZ Z NC C PO PE P M Z=0 Z=1 Cy=0 Cy=1 P=0 P=1 S=0 S=1 000 001 010 011 100 101 110 111 UNCONDITIONAL THEY ARE PROGRAM SPECIFIC

JMP ADDR JC ADDR CALL ADDR RET

LOGICAL GROUPS
ANA ORA ORM XOR CMA R R R R

STACK INPUT/OUTPUT &

M/C CONTROL GROUP
PUSH Rp = SP-1 Rh / SP-2 Rl [SP=SP-2] PUSH PSW :: M(SP-1) , (A) :::FLAG WORD M(SP-2) POP PSW Rl (SP) Rh (SP+1)::: SP=SP+2 (SP) (H) [(SP)+1]

XTHL:: (L)

IN Port(input) (A ) DATA OUT Port (output) DATA (A)

STACK INPUT/OUTPUT &

M/C CONTROL GROUP
EI = ENABLE INTRUPT

DI =DISABLE INTRUPT
HLT =HALT NOP = NO OPERATION RIM= READ INTRPT MASK