Cng PIC(Peripheral Interface Controller) l IC lp trnh dng iu khin cc thit b t ng vi cc b nh chng trnh (Flash ROM) v b nh m (SRAM).

. C th xem PIC l mt my tnh nh do trong PIC c b phn phn tch m lnh. Nh vy c th xem PIC l mt IC n phin, ngha l mt mnh n c th cu to thnh mt thit b vi iu khin hon chnh. B nh trong PIC c dung lng nh, tn s ti a xung nhp ca PIC l 20MHz v dung lng b nh t 1k-4k. Phn 1:Gii thiu khi qut v PIC 16F84A. Cc c tnh: Ch dng 35 cu lnh vit tt c cc chng trnh ngun cho PIC 16Fxx. Tt c cc cu lnh ch dng mt chu k my, cc cu lnh nhy dng 2 chu Tc vn hnh: dng xung nhp l 20MHz v chu k my l 200ns. C b nh chng trnh l(Flash Program Memory) 1024 Words(1k*14) B nh Ram (RAM Files Register)68 Byte. B nh d liu EEPROM 64 byte Chiu rng cu lnh l 1Word 14bit. X l d liu dng 8 bit C 15 thanh ghi chuyn dng SFR(Special Function Register) trong Ram. Dng ngn xp c chiu su 8 lp. C mode truy cp theo a ch trc tip , gin tip v a ch tng i. C 4 dng ngt: Ngt ngoi trn tn hiu chn RB0/INT; Ngt theo bit bo

k my.

trn ca Timer0; Ngt theo s thay i trn cc chn RB4, RB5, RB6, RB7, Ngt khi xong d liu vo EEPROM. chn). C 13 chn dng xut nhp d liu ( Port A c 5 chn v Port B c 8

Cng C kh nng cp dng chy vo/ chy ra ln: 25 mA, cp cho cc Led C 1 ng h Timer 0, dng thanh m xung 8 bit nn m c ti a 256 Vi b nh chng trnh Flash Program Memory c th xa ghi 1000 ln. D liu ct gi trong b nh EEPROM c th ln n 40 nm. C th lp trnh v np ngay trn Bo(ICSP-In Curcuit Serial Programing) ch C chc nng POR( Power On Reset), PWRT(Power-Up Timer), Chc nng Watch-dog(WDT) lm vic vi mch dao ng RC ring cho IC C mode bo v m(Code Protection) C nhiu ty chn cho mch dao ng xung nhp chnh. Lm vic vi mc ngun nui t 2 n 5.5v.

chiu sng. nhp.

dng 2 ln. OST(Ossilator Start Up Timer)

Hnh 1: Cng dng ca cc chn trn IC.

Cng Gii thch cng dng ca cc chn: OSC1/CLKIN: l chn ng vo ca mch dao ng thch anh, nh tn cho xung nhp v cng l mt ng vo cho xung nhp. OSC2/CLKOUT: l chn ng ra ca mch dao ng thch anh v l ng ra ca xung nhp. MRCL(Master Clear) : l chn Reset, tc dng ca lnh Reset l tr chng trnh v a ch 0000h. Lnh tc dng mc p thp. RA4/TOCKI l chn a nhim, va lm chn xut nhp ca PORT A v li l chn ly xung cho thanh m ca Timer0( chn ny c cc Drain h). RB0/INT l chn a nhim va l chn xut nhp ca Port B v li l chn pht ng theo ngt ngoi . Cc chn Port B c th lp trnh c tr khng ln, dng lm ng vo, nhp trng thi ngoi vo PIC. RB1, RB2,RB3 l cc chn xut nhp ca Port B. RB4,RB5 l cc chn xut nhp ca Port B v pht ng ngt theo s thay i trn cc chn ny. R6: l 1 chn xut nhp ca Port B v pht ng ngt theo s thay i trn chn ny. N cn c th lp trnh dng chn ny pht xung nhp cho cng nng truyn d liu ni tip. R7 l 1 chn xut nhp ca Port B v pht ng ngt theo s thay i trn chn ny. N cn c th lp trnh dng chn ny trao i d liu dng cho cng nng truyn d liu ni tip. VSS l chn ni masses. VDD l chn ni vo ngun dng (2v n 5v). Hnh 2: Hnh v cho thy cc khi chc nng trong Pic16F84A.

Cng

Flash Program Memory c dung lng 1024 thanh nh , loi rng 14 bit(1Kx14). y ct gi cc m lnh ca chng trnh ngun. Cc m lnh c truy cp theo m a ch c trong thanh ghi PC (Program Counter). M lnh xut hin trn thanh ghi Instruction Register. Thanh ghi Program Counter dng ghi cc a ch ca m lnh ca b nh Flash ROM. Trong hot ng khi dng cc lnh nhy n cc chng trnh con th a ch hin ti s c tm thi cho ct gi trong cc thanh ghi ngn xp, y chiu su ngn xp ch c 8 lp(8 Level track).

Cng Ngn xp 8 Level Stack d n g l u g i c c m a c h c a c h n g trnh chnh khi trong chng trnh c dng lnh nhy. a ch ct vongn xp c th hiu nh dng lnh Push v a ch ly ra t ngnxp c th hiu nh dng lnh Pop. Instruction Register l thanh ghi m lnh, ng ra, m lnh c th chuyn n khi gii m Instruction Decode & Control to lnh iu khin. Hay chuyn n khi x l a knh Address Multiplex truy cp cc thanh nh trong b nh Ram(File Register). Instruction Decode &Control l khi gii m, xc nh tnh nng iu khin trong cu lnh, n tc dng vo khi nh trng thi cho IC. Khi ny gm c cc chc nng Power-up Timer, Power-On Reset, Watchdog Timer. Power-up Timer dng kch hot IC theo ng h Timer. Ossilator Starup Timer dng kch hot mch dao ng theo ng h Timer Watch-Dog timer dng vo ra mode theo ng h Timer, mt tnh nng dng tit kim in. Timing Generation l khi to xung nhp chnh. PIC 16F84A c th hot ng vi xung nhp 20 MHz. ng h timer 0 dng mt thanh m 8 bit to ra chc nng iu khin theo thi gian. N c th m ti a 256 nhp, khi thanh m y, bit bo trn s chuyn ln mc 1. Cc Port I/O( gm Port A c 5 chn v port B c 8 chn) dng xut nhp d liu. Nhiu chn cn c tnh an nhim nn ngoi cng nng xut nhp d liu n cn c nhiu cng nng khc nh cng nng nhp xung m trn chn RA4/TOCKI, cng nng ngt trn chn RB0/INT B nh d liu EEPROM DATA MEMORY y l b nh xa ghi c trn 1trieu ln, EEPROM c 64 thanh nh, vi rng 8 bit. truy cp d liu trong

Cng cc thanh nh m a ch s chuyn vo thanh ghi EEADR v d liu xut nhp trn thanh ghi EEDATA. B nh RAM file Register l b nh RAM c 68 thanh nh vi rng 8 bit trong c 12 thanh nh chuyn dng(SFR, Special Function Register), cc thanh nh cn li lm thanh nh ph dng (GPR-General Purpose Regisrer), cc thanh nh chuyn dng xc nh hot ng ca IC, cc thanh nh ph dng dng lm thanh nh tm. Khi IC mt ngun, cc d liu trong thanh nh tm u b mt. Ngi ta truy nhp d liu trong cc thanh nh ca Ram vi b ni a ch Ram addr (7 ng) v xut nhp d liu trn b ni Data Bus (8 ng). Thanh ghi FSR(File Select Register) dng truy tm d liu theo m a ch gin tip(Indirect Addess), dng b ni Indirect Addr(7 ng). Mux(Multiplex) l khi x l a nhim, n cung cp m cho khi tnh ton ALU ALU(Arithmetic Logic Unit) l khi thc hin cc php ton s hc v Logic. Khng c khi ny IC khng c gi l IC my tnh. Thanh ghi WREG(Work Register) l thanh ghi cng tc, n ct gi kt qu ca ALU Hnh 3: Tm hiu b nh Flash Program Memory (tc b nh EEPROM). Sau y, chng ta tm hiu cu trc thanh ghi b nh trong PIC 16F84A: Flash Memory c dng lu gi cc m lnh ca chng trnh ngun. y 1 Word l 14 bit. N c 1024

Cng thanh nh( gi l 1Kword). Khi IC b mt ngun cc d liu ct bn trong thanh nh s khng b mt. S ln xa ghi ca loi b nh ny khng qu 1000 ln. Chng ta bit mi thanh ghi s c xc nh theo mt m a ch . a ch khi u l 0000h. Ngi ta t chc cc thanh nh trong b nh Flash ROM nh sau: o Thanh nh c a ch 0000h (Reset Vector) l v tr nhy n ca chc nng

Reset. Khi IC va c cp in hay c tc dng ca cng nng Watch-Dog v bt c l do no khc tc dng Reset s cho chng trnh khi u tr li t a ch 0000h. o Thanh nh 0004h(Interrup Vector) dng cho chc nng ngt Khi dng ngt theo Timer 0, khi thanh m trn, bit bo trn chuyn ln mc 1, chng trnh s nhy v a ch ny. Tc dng ca cc ngt ngoi cng khin chng trnh nhy n a ch 0004h ny. o Thanh ghi 2007h( Configuration Word) dng xc nh hot ng c bn ca PIC, trong vng ny c cc bit dng xc nh cho Mode Power-Up Time, xc nh cho Mode Watch-Dog Timer cng dng chn iu kin lm vic ca mch dao ng. Cc thanh nh bn trn vng ny(Test Configuration Memory Space) c dng cho cng nng ci t chng trnh vo b nh. Khng th truy cp c cc thanh nh trong vng nh ny. o B nh EEPROM(Electrically Eraseable Programmable Read Only Memory). y l loi b nh ROM xa ghi bng mc p cao Vpp nn ni dung ghi ca cc thanh nh s khng b xa khi IC khng c cp in. Cc thanh nh ny c th cho xa ghi li nhiu ln, dung lng b nh l 64 byte (c 64 thanh nh), s ln xa ghi hn ch khong 1 triu ln. V l do ny b nh EEPROM

Cng khng c dng lm b nh tm thi nh RAM(c s ln xa ghi khng gii han), b nh EEPROM ch c ghi cc d liu t b thay i. D liu ghi trong b nh ny c th tn ti n 40 nm. Hnh 4: Tm hiu b nh SRAM Cc thanh nh ca b nh File Register ca RAM. y ngi ta dng chuyn di nh (chuyn bank) cho b nh ny. Mi di nh c dung lng l 80 byte( 80 thanh nh vi m a ch l 00h n 4fh). Trong IC vi iu khin n phin PIC 16F84A c hai di nh ( c hai bank, bank 0 v bank 1). B nh ny chia lm hai phn: phn u, ngi ta chia ly lm 12byte( tc 12 thanh nh c a ch t 00h n 0Bh) ca mi di dng lm cc thanh nh c dng (SFR) v dng n t bit 0/1 xc nh cc trng thi vn hnh ca PIC. nh iu kin cho vic xut nhp trn cc Port v cn nh cc iu kin khc na. C 16 thanh ghi khc nhau trong vng cha thanh ghi c dng (11 thanh trong bank 0 v 5 trong bank 1). Ni dung trong mi thanh ny dng qun l s vn hnh ca PIC. Mc d c tng cng 12 thanh ghi lu tr( file register) nhng 7 trong chng nm chung trong c hai bank.

Cng Cn li 68 byte( tc 68 thanh nh c a ch 0Ch n 4Fh) t byte th 13 tr ln c gi l cc thanh ghi ph dng(GPR-General Purpose Register), n c dng nh cc thanh nh tm thi dng ghi cc kt qu , d liu khi chng trnh ang chy. Ni dung trong cc thanh ghi ph dng GPR u ging nhau trong c hai di do vy vic dng bit chuyn bank 0 hay bank 1 cng ch c dng 68 byte m thi. Chng ta bit ni dung trong cc thanh ghi ph dng s b xa ht khi IC khng c cp in nn vi thanh ghi ny s ln xa ghi l khng hn ch. Trong mi thanh ghi ph dng SFR u c cc cng nng chuyn dng nh sau: IDF: Data memory contents by direct addressing. Ni dung d liu trong b nh xc nh theo a ch gin tip. TMRO: Timer Counter Thanh m ca 8 bit ng h Timer 0. STATUS: Flag of Caculation result . Cc bit c dng cho cc php ton FSR: Indirect Data Memory address pointer thanh ghi con tr ch d liu trong b nh theo m a ch gin tip. Port A Port A Data I/O. Gm 5 bit thp xc lp trn trng thi bit trn Port A. Port B Port B Data I/O. Gm 8 bit xc lp trn trng thi bit trn Port B. EEData Data EEPROM. Thanh ghi d liu dng cho b nh EEPROM. EEDR Address for EEPROM. Thanh ghi b nh dng cho iah ch EEPROM. PCLATH Write buffer for upper 5 bit of the program counter. Thanh ghi m dng ghi 5 bit cao dng cho thanh ghi PC. INTCON : Interruption Control, dng 8 bit xc nh tnh nng ngt. OPTIN_REG Mode set . Gm 8 bit dng khai bo cc mode cho PIC. TRISA Mode set for PORTA Thanh ghi 5 bit dng xc dnh hng chuyn d liu cho Port A. TRISB Mode set for PORTB Thanh ghi 8 bit dng xc nh ng chuyn d liu cho Port B.

Cng EECON1 Control Register for EEPROM Thanh ghi iu khin vic ghi c cho EEPROM. EECON 2 Write Protection Register for EEPROM Thanh ghi 2 dng iu khin b nh EEPROM. Hnh 5. Thanh ghi STATUS

ngha ca tng bit trong thanh ghi STATUS Bit 7:IRP: Register Blank Select bit(use for indirect addressing). Bit chn di nh. Bit IRP khng dng vi PIC 16F84A. Sau lnh reset n xc lp li mc 0. Bit 6-5:RP1:RP0: Register Blank Select bit bit(use for indirect addressing). Cc bit dng chn di nh Bank 0 hay bank 1. Khi xc lp tr 00 l chn cc thanh nh di 0.( Bank 0 c a ch t 00h n 7fh). Khi xc lp tr 01 l chn cc thanh nh di 1.( Bank 1 c a ch t 80h n ffh).

Cng Bit 4: /TO: Time out bit. Bit bo thot ra trng thi Power-Up, trng thi Watchdog, trng thi Sleep. c xc lp mc 1, sau Power-up, dng lnh CLRWDThay lnh SLEEP. c xc lp mc 0, Khi thot ra trng thi WDT. Bit 3: /PD: Power-down bit: Bit bo trng thi gim mc ngun. c xc lp mc 1, sau Power down hay sau lnh CLRWDT. c xc lp mc 0, sau Power down hay sau lnh Sleep. Bit 1: DC:Ditgit carry/borrow bit Bit xc lp trng thi trn trong php ton cng s(trong cu lnh ADDWF hay cu lnh ADDLW) hay s mn trong php ton tr s. c xc lp mc 1 khi xut hin trn s bit th 4. c xc lp mc 0 khi khng c trn s bit thp th 4. Bit 0: C: c xc lp trng thi trn trong php ton cng( trong cu lnh ADDWF hay cu lnh ADDLW) hay s mn trong php ton tr. c xc lp mc 1 khi xut hin trn thanh ghi. c xc lp mc 0 khi khng c s trn thanh ghi. Hnh 6: Thanh ghi Option.

Tm hiu ngha cc bit trong thanh ghi Option-REG. Bit 7: -RBPU: PORTB Pull up Enable bit. Bit xc nh trng thi treo ca Port B

Cng c xc lp mc 1, khng cho treo PORT B. c xc lp mc 0, cho cc treo PORT B. Bit 6: INTEDG: Interrupt Edge Select Bit: Bit dng chn cnh ca xung dng cho chc nng ngt. c xc lp mc 1, pht ng ngt bng cnh ln caxung trn chn RB0/INT. c xc lp mc 0, pht ng ngt bng cnh xungca xung trn chn RB0/INT. Bit 5: TOCS: TMR0 Clock Source Select bit. Bit chn ngun xung cho mch in ng h Timer 0. c x c l p m c 1 , m c h n g h l m v i c v i x u n g vo trn chn RA4/T0CKI. c xc lp mc 0, khi mch in ng h dng xung ni Bit 4: TOSE: TMR0 Source Edge Select bit Bit chncnh ca ngun xung ly vo mch m ca mch in ng h Timer 0 c xc lp mc 1, vi cnh t mc cao xung mc thp trn chn RA4/T0CKI. c xc lp mc 0,vi cnh t mc thp ln mc cao trn chn RA4/T0CKI. Bit 3: PSA: Prescaler Assignment bit Bit xc nh tnh nng chn nh trc cho mch in Watch-dog v mch in ng h Timer 0. c xc lp mc 1, cho xc lp trc vi mch inWDT (Watch-dog). c xc lp mc 0, cho xc lp trc vi mch inTMR0 (Timer 0). Bit 2-0 : PS2:PS0: Prescaler Rate Select bits Cc bit dng chn tc cho Timer 0 v Watch-dog. Tr 3 ca bit 000 Tc vi TMR0 1:2 Tc ca WDT 1:1

001

1:4

1:2

Cng 010 011 100 101 110 111 1:8 1:16 1:32 1:64 1:128 1:256 1:4 1:8 1:16 1:32 1:64 1:128

Hnh 7: Thanh ghi INTCON

ngha ca tng bit trong thanh ghi INCONT( c a ch 0Bh-8Bh).

Cng Bit 7: GIE: Global Interrupt Enable bit Bit xc nh iu kin cho m tt c cc ngt hay tt tt c cc ngt. c xc lp mc 1, cho dng tt c cc ngt. c xc lp mc 0, cho tt tt c cc ngt. Bit 6: EEIE : EE Write Complete Interrupt Enable bit. Bit cho php tt m dng ngt sau khi ghi xong vo b nh EEPROM. c xc lp mc 1, cho m ngt khi ghi xong v b nh EEPROM. cxc lp mc 0, cho tt ngt ny Bit 5: TOIE: TMR0 Overflow Interrupt Enable bit. Bit cho tt m dng ngt theo bit bo trn ca thanh m trong mchin ng h Timer 0. c x c l p m c 1 , c h o m n g t t h e o b i t b o t r n c a mch in ng h. cxc lp mc 0, cho tt ngt ny Bit 4: TNIE: RB0/INT Interrupt Enable bit. Bit cho tt m dng ngt ngi trn chn RB0/INT. c xc lp mc 1, cho m ngt ngi vi tn hiu ngttrn chn RB0/INT. c xc lp mc 0, cho tt ngt theo dng ny. Bit 3: RBIE: RB Port Change Interrupt Enable bit Bit cho tt m dng ngt khi chuyn i RB bn cng Port B. c xc lp mc 1, cho m dng ngt ny. c xc lp mc 0, cho tt dng ngt ny. Bit 2: TOIF: TMR0 Overflow Interrupt Flag bit Bit xc nh ngt theo bit c trn ca ngt theo dng trn ca Timer 0 c xc lp mc 1, khi TMR0 trn, c xc lp mc 0 khi TMR0 cha trn. Bit 1: INTF: RB0/INT Interrupt Flag bit Bit xc nh ngt theo bit c ca dng ngt ngi trn chn RB0/INT c xc lp mc 1, khi ngt theo dng RB0/INT xy ra.c xc lp mc 0, khi ngt theo dng RB0/INT khng xy ra. Bit 0: RBIF: RB Port Change Interrupt Flag bit. Bit xc nh ngt theo bit c ca dng ngt theo chuyn i bncng RB.

Cng c x c l p m c 1 , k h i m t t r o n g R B 7 : R B 4 t h a y i (phi xa bng phn mm ). c xc lp mc 0, khi khng c thay i trng thi RB7:RB4. 2.3 PCL v PCLATH B m chng trnh(PC-Program Counter) quy nh c th a ch ca cc lnh. Cc lnh ny c ly v thc hin. rng PC l 13 bit. Byte thp c gi l thanh ghi PCL-n c th c v vit c. Byte cao c gi l thanh ghi PCH, thanh ghi ny c PC<12:8> bit v khng c v vit chng trnh c. Tt c cc lnh a ln thanh ghi PCH u c thng qua mt thanh ghi khc, gi l PCLATH( Program Counter Latch Hight). PCLATH s dng cc lnh Goto v Call c th truy cp bt k ni no trong b nh m ca PIC. 2.3.1. Stack Trong khoa hc my tnh mt ngn xp( cn c gi l b xp chng) l mt cu trc d liu tru tng hot ng theo nguyn l vo sau ra trc. i vi PIC 16F84A stack cho php kt hp 8 ln gi v ngt chng trnh. Stack c 8 cha, mi cha c rng 13 bit. D liu c th a vo stack bt k lc no khi thc hin mt lnh Call hoc mt lnh ngt xy ra trn mt cha. Trong stack c 2 php ton c bn : Push v Pop. Push b sung mt phn t vo nh ca Stack ngha l sau cc phn t c trong Stack.Pop gii phng v tr v phn t ang ng nh ca Stack. Tuy cc i tng c th thm vo bt k lc no nhng ch c i tng sau cng mi c th ly ra khi Stack. Sau khi Stack hon thnh xong 8 ln np d liu( i tng) th ln th 9 s vit chng ln cc d liu c a vo ln u, ln th 10 s vit chng ln cc d liu c a vo ln th hai.