MlC8C8CCLSSC8 8086

W 1he 8086 was Lhe flrsL 16b|t m|croprocessor lnLroduced by lnLel ln

1978
W lL ls lmplemenLed ln nMCS ( n|gh dens|ty short channe| MCS)
techno|ogy
W lL ls packaged ln a p|n CL8ul or plasLlc package
W lL ls avallable ln Lhree clock raLes
886 |n SMhz
8862 |n 8Mhz and
8861 |n 1Mhz
W 8086 operates |n both s|ng|e processor and mu|t|p|e processor
conf|gurat|on Lo achleve hlgh performance levels
W lL has 2address bus and hence can access as much as 1M8(2
2
)
memory locaLlons
W lL has 16b|t data bus
886 IN1LkNAL 8LCCk DIAGkAM
DNC1ICNAL 8LCCk DIAGkAM C 886
8086 Mlcroprocessor ls dlvlded lnLo Lwo
lndependenL funcLlonal parLs
W us lnLerface unlL (lu)
W LxecuLlon unlL (Lu)
8DS IN1LkACL DNI1
W 1he bus lnLerface unlL hand|es a|| transfer of
data and addresses on the buses for Lhe
LxecuLlon unlL
W 1hls unlL sends out addresses fetches
|nstruct|ons from memory reads data from
ports and memory and wr|tes data to ports
and memory
DILkLN1 Ak1S C 8ID
W SLGMLN1 kLGIS1LkS
W INS1kDC1ICN CIN1Lk
W 1nL DLDL
SLGMLN1 kLGIS1LkS
lu conLalns four 16blL segmenL reglsLers as
follows
W Code segmenL (CS) reglsLer
W SLack segmenL (SS) reglsLer
W LxLra segmenL (LS) reglsLer
W uaLa segmenL (uS) reglsLer
DNC1ICN C SLGMLN1 kLGIS1LkS
W ln 8086 compleLe 1M memory ls dlvlded lnLo 16 loglcal segmenLs
W Lach segmenL Lhus conLalns 64 k of memory
W Whlle addresslng any locaLlon ln Lhe memory bank Lhe hys|ca| address ls
calculaLed from Lwo parLs Lhe flrsL parL ls Segment address and Lhe
second ls Cffset
W 1he segmenL reglsLers conLaln 16blL segmenL base addresses relaLed Lo
dlfferenL segmenLs
W 1hus Lhe CS uS LS SS segmenL reglsLers respecLlvely conLaln Lhe
segmenL addresses for Lhe Code uaLa LxLra and SLack segmenLs
W 1hey may or may noL be physlcal separaLed
W Lach segmenL reglsLer conLalns a 16blL base address LhaL polnLs Lo Lhe
lowesLaddressed byLe of LhaL parLlcular segmenL ln memory
GLNLkA1ICN C nSICAL ADDkLSS
SegmenL address 1003P
CffseL address 3333P
SegmenL address1003P 0001 0000 0000 0101
ShlfLed by 4blL poslLlons0001 0000 0000 0101 0000
+
CffseL address 0101 0101 0101 0101
hyslcal address 0001 0101 0101 1010 0101
1 S S A S
INS1kDC1ICN CIN1Lk
W lL ls 16blL reglsLer whlch ldenLlfles Lhe locaLlon
of Lhe nexL word of lnsLrucLlon code LhaL ls Lo be
feLched ln Lhe currenL code segmenL
W l conLalns an offseL lnsLead of Lhe acLual address
of Lhe nexL lnsLrucLlon
W 1he 20blL address produced afLer addlLlon of Lhe
offseL sLored ln l Lo segmenL base address ln Lhe
CS ls called Lhe hyslcal address of Lhe code byLe
1nL DLDL
W 1he lasL secLlon of lu ls Lhe lllC group of
reglsLers called a queue lL ls baslcally a group of
reglsLers
W 1hls arrangemenL makes posslble for Lhe lu Lo
feLch Lhe lnsLrucLlon byLe whlle Lu ls decodlng an
lnsLrucLlon or execuLlng an lnsLrucLlon whlch
does noL requlre use of buses
W 1hls arrangemenL ls called plpellnlng
W 1hls ls done Lo speed up Lhe program execuLlon
LkLCD1ICN DNI1
W lL Lells Lhe lu where Lo feLch lnsLrucLlons or
daLa from
W uecodes Lhe lnsLrucLlon
W LxecuLes lnsLrucLlons
DILkLN1 Ak1S C LD
W u
W uecoder
W ConLrol ClrculLry
W Ceneral purpose reglsLers
W llag reglsLer
W olnLer and lndex reglsLers
ALD
1he Lu has 16blL arlLhmeLlc and loglc unlL
whlch can add subLracL -u C8 xC8
lncremenL decremenL complemenL or shlfL
blnary numbers
DLCCDLk
1he decoder ln Lhe Lu LranslaLes lnsLrucLlon
feLched from Lhe memory lnLo a serles of
acLlons whlch Lhe Lu carrles ouL
CCN1kCL CIkCDI1k
W Lu conLalns conLrol clrculLry whlch dlrecLs
lnLernal operaLlons
W lL also generaLes Lhe necessary Llmlng and
conLrol slgnals
IAkICDS kLGIS1LkS IN LD
GLNLkAL DkCSL DA1A kLGIS1LkS
W 1here are elghL 8blL general purpose reglsLers
ln 8086 labeled P P CP C uP
and u
W 1hese reglsLers can be used lndlvldually for
Lemporary sLorage of 8blL daLa
W 1he reglsLer ls also called Lhe accumulaLor
GLNLkAL DkCSL DA1A kLGIS1LkS
W CerLaln palrs of Lhese general purpose reglsLers
can be used LogeLher Lo sLore 16blL daLa words
W 1he accepLable reglsLer palrs are P and P
and CP and C uP and u
W 1he P palr ls called x reglsLer P palr ls
called x reglsLer CPC palr ls called Cx reglsLer
and uPu palr ls called ux reglsLer
W ny of Lhese reglsLers can be used as Lhe source
or desLlnaLlon of an operand durlng an arlLhmeLlc
and loglcal operaLlon
LAG kLGIS1Lk
W lL ls a 16blL sLaLus reglsLer wlLhln Lhe Lu of
8086
W 1here are nlne flags ln 8086
W Slx of Lhese are sLaLus flags and Lhree are
conLrol flags
886 LAG kLGIS1Lk
S1A1DS LAGS
W Cl lL ls seL Lo 1 lf carry ouL of MS
W l lL ls seL Lo 1 lf resulL has even parlLy
W l used for Cu
W Zl lL ls seL Lo 1 lf resulL ls 0
W Sl lL ls seL Lo 1 lf resulL ls negaLlve
W Cl lL ls seL Lo 1 lf slgned resulL ls ouL of Lhe
range
CCN1kCL LAGS
W 1l lL ls seL lf slngle sLep mode(debugglng)
W ll lf seL lnLerrupL requesL aL Lhe l-18 lnpuL of
8086 wlll be recognlzed
W ul lf seL sLrlng lnsLrucLlon auLomaLlcally
decremenLs Lhe address (sLrlng daLa Lransfers
proceed from hlgh address Lo Lhe low address
CIN1Lk AND INDLk kLGIS1LkS
W 1here are Lwo polnLer and Lwo lndex reglsLers
ln Lhe Lu of 8086
W 1hese reglsLers are used Lo sLore Lhe offseL
addresses of memory locaLlons relaLlve Lo Lhe
segmenL reglsLers
CIN1Lk kLGIS1Lk
1wo polnLer reglsLers are
W SLack polnLer 1he value ln Lhe S always
represenLs Lhe offseL of Lhe nexL sLack locaLlon
LhaL can be accessed
W ase polnLer lL also represenLs an offseL
relaLlve Lo SS reglsLer buL ls employed ln Lhe
based addresslng mode of 8086
INDLk kLGIS1Lk
1wo lndex reglsLers are
W Source lndex (Sl) lL ls used Lo sLore an offseL
address for source operand
W uesLlnaLlon lndex (ul) lL ls used for sLorage of
an offseL address for Lhe desLlnaLlon operand