ECE556: Design Automation

of Digital Systems
Spring 2007
Instructor: Azadeh Davoodi

Lecture 1
January 23, 2007

Course Information
• Lectures: RT 9:30am-10:45pm, 2540 EH
• Web address:
http://www.ece.wisc.edu/~adavoodi/
• Office: 4621 Engineering Hall
• Office hours: TR 11:00am-12:00pm
• Information on academic dishonesty

1
 Textbooks
• Main textbook
Sabih H. Gerez, “Algorithms for VLSI Design
Automation”, Wiley, 1999
– does not discuss all the topics in CAD tools and is
relatively old, however provides depth in many core
topics
• Optional:
S. Sait, H. Youssef, “VLSI Physical Design
Automation: Theory and Practice”, World Scientific,
1999
– can be used as supplementary reading for the
physical design lectures
3

Prerequisites
• Elementary knowledge of C or C++
programming
• Some familiarity with digital IC design
– suitable for CS students as well as EE and CE
students
• Elementary knowledge of algorithms

2
 Grading
• Midterm (20%)
• Final (30%)
• Homework (25%)
– almost biweekly home works
– include paper home works, programming assignments,
and home works on using academic/commercial tools
– late homework policy: each day late 20% off
• Class project (25%)
– implement a CAD tool (details will be posted soon)
• Effective class participation (up to 5% bonus)
5

The VLSI Design Problem

• What is VLSI?
– Very Large Scale Integration: IC with more
than 10^5 transistors (close to 1 billion
transistors exist in cutting-edge ICs today!)
• Examples of VLSI circuits:
– general purpose IC such as microprocessors,
DSPs, memories
– Application Specific ICs (ASICs) used for
narrow range application
6

3
 The VLSI Design Problem
• VLSI design problem: realize a given
specification on silicon with the following
requirements:
– optimize the following metrics
• area
• yield
• power dissipation
• speed
• design time
• testability
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• etc.

Silicon Compilation
Analogy with compilers for programming languages:
from algorithm to machine instructions

In VLSI:
from algorithm to mask patterns

• Current practice:
– still far away from a single push-button operation
– Q: What is the difference between EDA (Electronic
Design Automation) and CAD (Computer-Aided Design)?

4
 Design for Conflicting Metrics
• Area
• Yield (percentage of working chips)
– causes of failure: manufacturing defects
• Power dissipation (trades-off with area)
– important in battery-operated portable devices
– relates to heat dissipation
• Speed (trades-off with power and area)
• Design time
– need to have quick time-to-market or turn-around-time for
economical purpose
– Q: give examples of ways to reduce the design time?
• Testability (trades-off with area)
– need techniques to quickly find the defective chips after
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fabrication

Hierarchy and Abstraction

• Optimization cannot be done in one step
– partition problem and optimize subproblems
– notion of hierarchical design and abstract
representation help deal with the design
complexity
• Hierarchy: shows structure of design at different
levels of abstraction
• Abstraction: when looking at a certain level, you
don’t need to know all details of the lower levels

10

5
 Hierarchy and Abstraction:
A
Example
A Level 1
B D
E F
M N B C D Level 2
G H O
J Level 3
I C E F G H I M N O
K J Level 4
L K L
decomposition tree
(a) (b)

A
A C E F I M N
B D I
J
C G H K L O

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(c) (d) (e)

Design Domains
• Design domains:
– behavioral: black box view
• relation between input and output given without a reference to
the implementation of these relations
– e.g., describing behavior of several transistors using logical
expressions and truth tables
– Q: what is the behavioral description at transistor level?
– structural: interconnection of sub-blocks
• subcircuits used and their interconnections
• e.g., transistor-level circuit describing a NAND gate
– physical: location of structural components on the chip
• e.g., location of a NAND gate or rout of an interconnect on the
2D chip area
• Each design domain has its own hierarchy
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6
 Gajski’s Y-Chart and
Relation with Design Methodology
BEHAVIORAL DOMAIN STRUCTURAL DOMAIN
Systems
Algorithms Processors
Register transfers ALU’s, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer functions Transistors

Transistor layout
Cell layout
Module layout
Floorplans
Physical partitions
PHYSICAL DOMAIN
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A design methodology defined depending on the way the Y-chart is traversed

Top-Down Design Methodology

BEHAVIORAL DOMAIN STRUCTURAL DOMAIN
Systems
Algorithms Processors
Register transfers ALU’s, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer functions Transistors

Transistor layout
Cell layout
Module layout
Floorplans
Physical partitions
PHYSICAL DOMAIN
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7
 Top-Down Structural Design /
Bottom-Up Layout Construction
BEHAVIORAL DOMAIN STRUCTURAL DOMAIN

Systems
Algorithms Processors
Register transfers ALU’s, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer functions Transistors

Transistor layout
Cell layout
Module layout
Floorplans
Physical partitions
PHYSICAL DOMAIN 15

Design Actions
• Synthesis: increasing information about the
design by providing more detail
• Verification: checking whether a synthesis step
has left the specification intact
• Analysis: collecting information on the quality of
the design
• Optimization: increasing the quality of the design
by rearrangements in a given description
• Design Management: storage of design data,
cooperation between tools, design flow, etc.
16

8
 Top-Down Synthesis
High-Level
Synthesis

Logic
Synthesis

Physical
Design (synthesis)

Fabrication and
Packaging
17

Algorithm, System and High-Level Synthesis

Logic Synthesis

Transistor-Level Synthesis

Physical
Design

18

9
High-Level & Logic Synthesis
a multi-stage process

Specification
Logic Extraction
module example(clk, a, b, c, d, f, g, h)
input clk, a, b, c, d, e, f;
Technology-Independent
aoutput g, h; reg g, h; Optimization
b a Technology-Dependent Mapping
h
ealways @(posedge
g = a | b;
clk) begin g1
0 G
bif (d) beging0
if (c) h = a&~h;
f
else h = b; h5 g
G
dc if (f) g = c; else a^b;
end else h3 g
b if (c) h = 1; else h ^b; H
end e d
fendmodule h1 H h
ae
c c clk
d
f
clk
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© Prof. Ciesielski

Physical Design (Synthesis)

Circuit
Design

Partitioning

Floorplanning
&
Placement

Routing

Compaction

Fabrication
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10
 Design Styles
• Can the designer control the shape of all
mask patterns?
– Yes, full-custom fabrication
– No, semi-custom fabrication, e.g. gate array,
sea of gates
• Can the designer specify the design up to
the level of individual transistors?
– Yes, full-custom design
– No, semi-custom design e.g. by means of
standard cells, module generators, etc.

21

Design Styles
Design Styles

Semi-Custom

Full-Custom Standard-Cell Gate Arrays FPGA

22

11
Design Styles – Full Custom

Mask layout of the Intel 486 microprocessor chip 23

Design Styles – Standard Cell

24

12
Design Styles – Gate Arrays

25

Design Styles – FPGAs

26

13
 Design Styles Trade-offs

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Course Objectives
• Show design automation methodology
– discuss the approaches to solve the VLSI problem
• Show inside the VLSI design tools
– understand functionality and algorithms, challenges
and limitations of the tools
– understand what tasks can or can not be performed
by the CAD tools
– understand why some problems can only be
approximately solved after long computations while
others are exactly solved in short time
• Provide introduction for students interested to
specialize in development of these tools 28

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 Course Timeline
Preliminaries:
CMOS technology, 6 lectures, paper home works
Algorithmic graph theory,
Optimization methods

High-level Synthesis 4 lectures, programming assignment

4 lectures, programming assignment,

Logic Synthesis
paper home works

11 lectures, programming
Physical Synthesis assignment, paper home works

Simulation 2 lectures, paper home works

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