INSPEC

‫מבנה רשומה מקוצר במאגר‬

Accession
Number 8894588
Author Shih-Hao Ou. Tay-Jyi Lin. Chao-Wei Huang. Yu-Ting
Kuo. Chie-Min Chao. Chih-Wei Liu. Chein-Wei Jen.
Author/Editor Dept. of Electron. Eng., Nat. Chiao Tung Univ.,
Affiliation Taiwan.
Title A 52mW 1200MIPS compact DSP for multi-core
media SoC.
Source Proceedings of the ASP-DAC 2006. Asia and South
Pacific Design Automation Conference 2006 (IEEE
Cat. No.06EX1199C). IEEE. 2005, pp. 2.
Piscataway, NJ, USA.
Conference Proceedings of the ASP-DAC 2006. Asia and South
Information Pacific Design Automation Conference 2006.
Yokohama, Japan. 24-27 Jan. 2006.
Abstract This paper presents a DSP core for multi-core
media SoC, which is optimized to execute a set of
signal processing tasks very efficiently. The fully-
programmable core has a data-centric instruction
set and a corresponding latency-insensitive micro-
architecture, where the hardware design is
optimized concurrently with its automatic software
generator. The proposed DSP core has 3
performance (in cycles) of those found in
commercial dual-core application processors with
similar computing resources. The silicon
implementation in UMC 0.18mum 1P6M CMOS
technology operates at 314MHz and