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ARM Instruction Set Quick Ref
ARM Instruction Set Quick Ref
Addressing Mode 5 - Coprocessor Data Transfer Processor Modes Prefixes for Parallel Instructions
Pre-indexed Immediate offset [Rn, #+/-<immed_8*4>]{!} 16 User S Signed arithmetic modulo 28 or 216, sets CPSR GE bits
Zero offset [Rn] Equivalent to [Rn,#0] 17 FIQ Fast Interrupt Q Signed saturating arithmetic
Post-indexed Immediate offset [Rn], #+/-<immed_8*4> 18 IRQ Interrupt SH Signed arithmetic, halving results
Unindexed No offset [Rn], {8-bit copro. option} 19 Supervisor U Unsigned arithmetic modulo 28 or 216, sets CPSR GE bits
23 Abort UQ Unsigned saturating arithmetic
27 Undefined UH Unsigned arithmetic, halving results
31 System
ARM Addressing Modes
Quick Reference Card
Coprocessor operations § Assembler Action Notes
Data operations 2 CDP{cond} <copr>, <op1>, CRd, CRn, CRm{, <op2>} Coprocessor dependent
Alternative data operations 5 CDP2 <copr>, <op1>, CRd, CRn, CRm{, <op2>} Coprocessor dependent Cannot be conditional.
Move to ARM register from coprocessor 2 MRC{cond} <copr>, <op1>, Rd, CRn, CRm{, <op2>} Coprocessor dependent
Alternative move 5 MRC2 <copr>, <op1>, Rd, CRn, CRm{, <op2>} Coprocessor dependent Cannot be conditional.
Two ARM register move 5E* MRRC{cond} <copr>, <op1>, Rd, Rn, CRm Coprocessor dependent
Alternative two ARM register move 6 MRRC2 <copr>, <op1>, Rd, Rn, CRm Coprocessor dependent Cannot be conditional.
Move to coproc from ARM reg 2 MCR{cond} <copr>, <op1>, Rd, CRn, CRm{, <op2>} Coprocessor dependent
Alternative move 5 MCR2 <copr>, <op1>, Rd, CRn, CRm{, <op2>} Coprocessor dependent Cannot be conditional.
Two ARM register move 5E* MCRR{cond} <copr>, <op1>, Rd, Rn, CRm Coprocessor dependent
Alternative two ARM register move 6 MCRR2 <copr>, <op1>, Rd, Rn, CRm Coprocessor dependent Cannot be conditional.
Load 2 LDC{cond} <copr>, CRd, <a_mode5> Coprocessor dependent
Alternative loads 5 LDC2 <copr>, CRd, <a_mode5> Coprocessor dependent Cannot be conditional.
Store 2 STC{cond} <copr>, CRd, <a_mode5> Coprocessor dependent
Alternative stores 5 STC2 <copr>, CRd, <a_mode5> Coprocessor dependent Cannot be conditional.