1.

Lab 1: Building Hierarchy

INP[0] INP[1] INP[2] INP[3]
MY_AND2

U0
MY_AND2

SIG Top level: AND_OR 1

MY_OR2

OUT1

U1

SIG 2

U2

Figure 1

Create the Verilog HDL file.

// MY_OR2 `timescale 1ns/1ps module MY_OR2(a, b, out); input a, b; output out; assign out = a | b; endmodule //MY_AND2 `timescale 1ns/1ps module MY_AND2(a, b, out); input a, b; output out; assign out = a & b; endmodule //AND_OR `timescale 1ns/1ps module AND_OR(INP, OUT1); input [3:0] INP; output OUT1; wire sig1; wire sig2; MY_AND2 U0 (.a (INP[0]), .b (INP[1]), .out (sig1));

MY_AND2 U1 (.a (INP[2]), .b (INP[3]), .out (sig2)); MY_OR2 U2 (.a (sig1), .b (sig2), .out (OUT1)); endmodule

ModelSim compile

2. Lab 2: Simulation/Verification
write a Verilog testbench for the AND_OR

Figure 2

Create the Verilog HDL file

module and_or_Testbench; // Inputs wire [3:0] INP; reg [1:0] A_STIM = 2'b00; // These wires drive input bus INP reg [1:0] B_STIM = 2'b00; wire OUT1; // Outputs assign INP = {A_STIM, B_STIM}; // This concatenates the two wires to drive INP. AND_OR dut (.INP(INP), .OUT1(OUT1)); initial begin // Initialize Inputs Add stimulus A_STIM = 2'b00; #200 A_STIM = 2'b01; #200 A_STIM = 2'b11; #200 A_STIM = 2'b10; end always #100 B_STIM = B_STIM + 1; endmodule