Processor Architecture: Direct Execution RISC Processor

I wonder where this goes?

ALU

Bet t a K strucmiorny o n Iit e M

0
A

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Performance Measure MIPS =

= Millions of Instructions Per Second PUSHING PERFORMANCE ... TODAY: __________________ CPI NEXT: ___________________ MHz
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Clock Frequency (MHz)

C.P.I.
= __________________ per __________________

The BETA Instruction Set Architecture

OPCODE

6
1 0 x x x x

5
Rc

5
Ra

5
Rb

16

11

Instruction classes -distinguished by OPCODE!

*optional

(unused)

Operate class: Rc <- <R a> o p < Rb >

1 1 x x x x

Rc

Ra

literal C (signed)

Operate class: Rc <- <R a> o p C O p c o d e s, b o t h f o r m a t s : ADD CMPEQ AND SHL SUB CMPLE OR SHR MUL* CMPLT XOR SRA DIV*

0 1 x x x x

Rc
LD: ST: JMP: BEQ: BNE: LDR:

Ra

literal C (signed)

Rc <- M e m[< Ra> + C ] M e m[< Ra >+C] <- Rc Rc <- < P C > + 4 ; P C <- < Ra> Rc <- < P C > + 4 ; i f < Ra > = 0 t h e n P C <- < P C > + 4 + ( C < < 2 ) Rc <- < P C > + 4 ; i f < Ra >

OP (eg, ADD) OPC (eg, ADDC) LD ST JMP BEQ / BNE LDR

t h e n P C <- < P C > + 4 + ( C < < 2 )

Rc <- < < P C > + 4 + ( C < < 2 ) >

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Approach: Incremental Featurism

Each instruction class can be implemented using a simple component repertoire. Well try implementing data paths for each class individually, and merge them (using MUXes, etc). Steps: 1. Operate instructions 2. Load & Store Instructions 3. Jump & Branch instructions 4. Exceptions 5. Merge data paths
A

Components:
RA1

ALU

Instruction Memory

WD A

RA2
RD R/W

Data Memory

WA WE WD

Register File (2-port)

RD1 RD2

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2 combinational READ ports, 1 clocked WRITE port

(independent Read addresses)
CLK

2-Port Register File

RA1
5

RA2

RA

Write Address Write Enable Write Data CLK

WA WE
32

RD

<A>

WD

Register File (2-port)

RD1
32

WE

WA

RD2
WD 32 new <A>

NB: <R31> Always ZERO!

(Independent Read Data)

What if (say) WA=RA1???

RD1 reads ______________________________!
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Starting point: ALU Operations

32-bit (4-byte) ADD instruction:
10000000100000100001100000000000 (unused) OpCode Rc Ra Rb

Means, to BETA,

R4

<R2> + <R3>

GOAL: Read next 32-bit instruction DECODE instruction: ADD, SUB, XOR, etc READ operands (Ra, Rb) from RF; PERFORM indicated operation; WRITE result (Rc) back into RF.
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Instruction Fetch/Decode
PC
00

Instruction Memory
D

+4

INSTRUCTION WORD FIELDS

Control Logic

CONTROL SIGNALS
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ALU Operations
PCIF
00

Instruction Memory
D

1 0 X X X X

Rc

Ra

Rb

unused

OP:

Rc <- <RA> op <RB>

+4

Ra <20:16>

Rb: <15:11>

RA1
Rc <25:21>

WAWA RD1

Register File

RA2 WD RD2 WE
WERF

Control Logic

A ALUFN

ALU

ALUFN WERF

NB: CPI = _________

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ALU Reg-Constant Operations

1 1 X X X X
PC
IF
00

Rc

Ra

literal C (signed)

OP:
A

Rc <- <RA> op sxt(C)

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11>

RA1 Rc <25:21> WA WA RD1

C: <15:0>

Register File

RA2 WD RD2 WE WERF

C: <15:0> sign-extended

BSEL

Control Logic

BSEL ALUFN WERF

ALUFN

ALU

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Load Instruction
0 1 1 0 0 0
PC
IF
00

Rc

Ra

literal C (signed)

LD:
A

Rc <- Mem[<Ra>+C]

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11>

RA1 Rc <25:21> WA WA RD1

C: <15:0>

Register File

RA2 WD RD2 WE WERF

C: <15:0> sign-extended

BSEL

Control Logic

BSEL WDSEL ALUFN Wr WERF

ALUFN

ALU

WD

R/W

Wr

Data Memory
Adr RD

WDSEL

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Store Instruction
0 1 1 0 0 1
PC
IF
00

Rc

Ra

literal C (signed)

ST:
A

Mem[<Ra>+C] <- Rc

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

RA2SEL

RA1 Rc <25:21> WA WA RD1

C: <15:0>

Register File

RA2 WD RD2 WE

WERF

C: <15:0> sign-extended

BSEL

Control Logic

RA2SEL
A B

BSEL WDSEL ALUFN Wr WERF

ALUFN

ALU

WD

R/W

Wr

Data Memory
Adr RD

WDSEL

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JT

JMP Instruction
1 0

PCSEL

0 1 1 0 1 1

Rc

Ra

literal C (signed)

JMP:
PC
IF
00

Rc <- <PC>+4; PC <- <Ra>

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

RA2SEL

RA1 Rc <25:21> WA WA RD1

C: <15:0>

Register File
JT
C: <15:0> sign-extended

RA2 WD RD2 WE WERF

BSEL

Control Logic
PCSEL RA2SEL
A B

BSEL WDSEL ALUFN Wr WERF

ALUFN

ALU

WD

R/W

Wr

Data Memory
Adr RD

<PC>+4

WDSEL

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BEQ/BNE Instructions
JT PCSEL
4 3 2 1 0

0 1 1 1 0 1
00

Rc

Ra

literal C (signed)

PC

IF

BEQ:
A

Rc <- <PC>+4; if <Ra>=0 then PC <- <PC>+4+(C<<2)

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

<PC>+4+C

RA2SEL

C: <15:0> << 2 sign-extended

Rc <25:21>

RA1 WA WA RD1 Z

Register File
JT
C: <15:0> sign-extended

RA2 WD RD2 WE WERF

C: <15:0>

Z
1 0 BSEL

Control Logic
PCSEL RA2SEL
ALUFN A B

ALU
Adr

WD

R/W

Wr

BSEL WDSEL ALUFN Wr WERF

Data Memory
RD

<PC>+4

WDSEL

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Load Relative Instruction

0 1 1 1 1 1 Rc Ra literal C (signed)

Hey, WAIT A MINUTE.

Whats Load Relative good for anyway??? I thought Code is PURE, i.e. READONLY; and stored in a PROGRAM region of memory; Data is READ-WRITE, and stored either On the STACK (local); or In some GLOBAL VARIABLE region; or In a global storage HEAP. So why an instruction designed to load data thats near the instruction???

LDR:

Rc <- <<PC> + 4+(C<<2)>

one ANS:_____________
C: BETA: X = X * 123456; LD(X, r0) LDR(c1, r1) MUL(r0, r1, r0) ST(r0, X) ... LONG(123456)
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c1:
6.004 Fall 97...

Load Relative Instruction

JT PCSEL
4 3 2 1 0

0 1 1 1 1 1
00

Rc

Ra

literal C (signed)

PC

IF

LDR:
A

Rc <- <<PC> + 4+(C<<2)>

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

RA2SEL

C: <15:0> << 2 sign-extended

Rc <25:21>

RA1 WA WA RD1 Z

Register File
JT
C: <15:0> sign-extended

RA2 WD RD2 WE WERF

C: <15:0> <PC>+4+C

Z
ASEL 1 0 1 0 BSEL

Control Logic
PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF <PC>+4
ALUFN A B

ALU
Adr

WD

R/W

Wr

Data Memory
RD

WDSEL

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Well, thats the Beta Instruction Set...

Opcode Map:
0 0 0 0 0 0 x xx 0 0 1 xxx 0 1 0 xxx 0 1 1 xxx 1 0 0 xxx 1 0 1 xxx 1 1 0 xxx 1 1 1 xxx
L D A DD A ND A DD C A ND C ST SUB OR SUBC OR C M U L * XOR M U L C* XOR C D IV C* J M P D IV * CM P E Q SHL CM P E Q C SHLC BEQ CM P L T S HR CMP L T C S HRC B NE CMPL E S RA CM P L E C S RA C LD R

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

... Anything weve forgotten?

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Exception Processing
Wed like RECOVERABLE INTERRUPTS for
FAULTS (eg, Illegal Instruction) - CPU or SYSTEM generated TRAPS & system calls (eg, read-a-character) - CPU generated I/O events (eg, key struck) - externally generated

GOAL: Interrupt running program, invoke exception handler (like a procedure call), return to continue execution. KEY: TRANSPARENCY to interrupted program. IMPLEMENTATION:
FORCED procedure call: new <PC>, save old <PC> for return. ... but WHERE to save old PC? Use LP?

APPROACH: Another reserved register, XP.

Why cant interrupted program use XP?
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XAdr

ILL OP

JT

Traps & Interrupts

1 0

PCSEL

PC

00

Exception: Bad OpCode:

A

XP <- <PC>+4; PC <- XAdr XP <- <PC>+4; PC <- IllOp

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

RA2SEL

WASEL C: <15:0> << 2 sign-extended XP Rc <25:21>

1 0

RA1 WA WA RD1 JT

Register File

RA2 WD RD2 WE WER F

<PC>+4+C*4 IRQ Z

C: <15:0>

C: <15:0> sign-extended

ASEL

BSEL

Control Logic
PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF WASEL
<PC>+4

A ALUFN

ALU
Adr

WD

R/W

Wr

Data Memory
RD

WD SEL

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Control Logic Truth Table

Since control logic is COMBINATIONAL, we can specify it via a truth table of the form ...
Control Logic Inputs: OPCODE Z IRQ Control Logic Outputs: PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF WASEL OP OPC LD ST BEQ BNE JMP LDR (Illegal)

YOU should be able to fill in this table!

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XAdr

ILL OP

JT

Scenario Sheet ...

1 0

PCSEL

PC

00

Instruction Memory
D

+4

Ra <20:16>

Rb: <15:11> 0 1

Rc <25:21>

+
Control Logic Inputs: OPCODE Z IRQ Control Logic Outputs: PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF WASEL

RA2SEL

WASEL C: <15:0> << 2 sign-extended XP Rc <25:21>

1 0

RA1 WA WA RD1 JT

Register File

RA2 WD RD2 WE WER F

<PC>+4+C*4 IRQ Z

C: <15:0>

C: <15:0> sign-extended

ASEL

BSEL

Control Logic
PCSEL RA2SEL ASEL BSEL WDSEL ALUFN Wr WERF WASEL
<PC>+4

A ALUFN

ALU
Adr

WD

R/W

Wr

Data Memory
RD

WD SEL

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