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    2-To-4 Decoder Circuit Library Ieee Use Ieee - STD - Logic - 1164.all Entity Decoder4 Is Port (S: in STD - Logic - Vector (1 Downto 0) X: Out STD - Logic - Vector (3 Downto 0) ) End Decoder4

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    AlliéAgatorRadeon
    This document contains code for three different circuit components: 1) A 4-to-2 decoder circuit that takes in a 2-bit input and outputs a 4-bit vector. 2) A black box component that takes in a 4-bit input and outputs a 4-bit vector, with logic to set the output to a specific value based on the input. 3) An ALU component that performs arithmetic and logical operations on two 4-bit inputs based on a 3-bit selection input, and outputs an 8-bit result. It contains a case statement to handle the different operations.

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    2-To-4 Decoder Circuit Library Ieee Use Ieee - STD - Logic - 1164.all Entity Decoder4 Is Port (S: in STD - Logic - Vector (1 Downto 0) X: Out STD - Logic - Vector (3 Downto 0) ) End Decoder4

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    AlliéAgatorRadeon
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    This document contains code for three different circuit components: 1) A 4-to-2 decoder circuit that takes in a 2-bit input and outputs a 4-bit vector. 2) A black box component that takes in a 4-bit input and outputs a 4-bit vector, with logic to set the output to a specific value based on the input. 3) An ALU component that performs arithmetic and logical operations on two 4-bit inputs based on a 3-bit selection input, and outputs an 8-bit result. It contains a case statement to handle the different operations.

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    This document contains code for three different circuit components: 1) A 4-to-2 decoder circuit that takes in a 2-bit input and outputs a 4-bit vector. 2) A black box component that takes in a 4-bit input and outputs a 4-bit vector, with logic to set the output to a specific value based on the input. 3) An ALU component that performs arithmetic and logical operations on two 4-bit inputs based on a 3-bit selection input, and outputs an 8-bit result. It contains a case statement to handle the different operations.

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    Download as DOC, PDF, TXT or read online from Scribd
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    Download as doc, pdf, or txt
    8 views4 pages

    2-To-4 Decoder Circuit Library Ieee Use Ieee - STD - Logic - 1164.all Entity Decoder4 Is Port (S: in STD - Logic - Vector (1 Downto 0) X: Out STD - Logic - Vector (3 Downto 0) ) End Decoder4

    Uploaded by

    AlliéAgatorRadeon
    This document contains code for three different circuit components: 1) A 4-to-2 decoder circuit that takes in a 2-bit input and outputs a 4-bit vector. 2) A black box component that takes in a 4-bit input and outputs a 4-bit vector, with logic to set the output to a specific value based on the input. 3) An ALU component that performs arithmetic and logical operations on two 4-bit inputs based on a 3-bit selection input, and outputs an 8-bit result. It contains a case statement to handle the different operations.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
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    of 4

    -- 2-to-4 decoder circuit library ieee; use ieee.std_logic_1164.

    all; entity decoder4 is port( s: in std_logic_vector(1 downto 0); x: out std_logic_vector(3 downto 0) ); end decoder4;

    LIBRARY ieee; USE ieee.std_logic.1164.all;

    ENTITY black_box Is PORT(input : IN std_logic_vector (3 downto 0); output : OUT std_logic_vector (3 downto 0)); END black_box;

    ARCHITECTURE behavior OF black_box IS BEGIN WITH input SELECT output <= 0001 when 0101,

    library IEEE; use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU is port( clk : in std_logic; enter_db : in std_logic; bilA : in std_logic_vector(3 downto 0); bilB : in std_logic_vector(3 downto 0); pilihan : in std_logic_vector(2 downto 0); hasil : out std_logic_vector(7 downto 0) ); end ALU; architecture Behavioral of ALU is signal temp : std_logic_vector(7 downto 0) := "00000000"; begin process(clk,enter_db,bilA,bilB,pilihan) begin if (clk'event and clk='1') then if (enter_db='1') then case pilihan is when "000" => -- (+) temp <= ("0000"&bilA) + ("0000"&bilB); when "001" => -- (-) temp <= ("0000"&bilA) - ("0000"&bilB); when "010" => -- (*) temp <= bilA * bilB; when "011" => --2s complement temp <= not("0000"&bilA) + 00000001; when "100" => --2s complement temp <= not("0000"&bilB) + 00000001; when "101" => temp <= ("0000"&bilA) AND ("0000"&bilB); when "110" => temp <= ("0000"&bilA) OR ("0000"&bilB); when "111" => temp <= ("0000"&bilA) XOR ("0000"&bilB); when others => temp <= "00000000"; end case; end if; end if; end process; hasil <= temp; end Behavioral;

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