MITS/.

/FILE02/2011-12/07
Madanapalle Institute of Technology and Science, Department of Electronics and Communication

LESSON PLAN
FACULTY NAME: ARUN S ACADEMIC YEAR: 2011-12 SEMESTER: I BRANCH: ECE B SEC SUBJECT: LDICA CLASS: III BTECH

BATCH: 1

Lecture No. 1 2 3 4 5 6 7

Date

Topic to be covered

MODULE 1 8/07/2011 Introduction 15/07/2011 OP AMP Applications Adder, Subtractor, Comparator Circuits. 22/07/2011 29/07/2011 5/08/2011 19/08/2011 26/08/2011 Active Filter Applications LPF, HPF (first order). Function Generator using OP AMPs. IC 555 Timer Monostable and Astable Operation Circuit. Voltage Regulator using IC 723. 4 bit DAC using OP AMP. MODULE 2

8 9 10 11 12 13 14 15

2/09/2011 Logic Gates- 74XX 09/09/2011 Half Adder, Full Adder 16/09/2011 23/09/2011 30/09/2011 14/10/2011 21/10/2011 Half Subtractor, Full Subtractor 3-8 Decoder -74138 & 8-3 Encoder- 74X148 8 x 1 Multiplexer -74X151 and 2x4 Demultiplexer-74X155. 4 bit Comparator-74X85. Barrel Shifter

28/10/2011 Revision Total No. of expected periods :45