--{*****************************************************************************

*}
--{ FileName............: Clock_div.vhd
--{ Project.............: FPGA
--{-----------------------------------------------------------------------------}
--{
--{ Component for dividing a clock
--{-----------------------------------------------------------------------------}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--{-----------------------------------------------------------------------------}
--{ Params : <CLK_TIMING_IN_NS> Speed (in ns) of input clock
--{
<CLK_TIMING_OUT_NS> Speed (in ns) of required output clock
--{
<CLK_IN>
Input clock
--{
<CLK_OUT>
Output clock
--{ Descript: Clock divider component
--{-----------------------------------------------------------------------------}
entity CLOCK_DIV is
generic(
CLK_TIMING_IN_NS : natural;
-- Input clock cycle
time (in ns)
CLK_TIMING_OUT_NS: natural
-- Input clock cycle
time (in ns)
-- Should be multiple
of CLK_TIMING_IN_NS otherwise actual timing is slightly less
);
port(
CLK_IN : in std_logic;
-- Input clock
CLK_OUT: out std_logic
-- Output clock
);
end CLOCK_DIV;
--{-----------------------------------------------------------------------------}
--{
Architecture
--{-----------------------------------------------------------------------------}
architecture CLOCK_DIV of CLOCK_DIV is
constant COUNTER_LOAD: natural := (CLK_TIMING_OUT_NS / CLK_TIMING_IN_NS / 2) 1; -- Required counts of the input clock to run at the required output speed
signal
ivision)
signal

counter: integer range 0 to COUNTER_LOAD;

-- Counter (clock d

toggle : std_logic := '0';

-- Toggle bit

begin
--{-----------------------------------------------------------------------------}
--{ Params : <CLK_IN> Clock
--{ Descript: Countdown and reload counter and toggle when counted down
--{-----------------------------------------------------------------------------}

process (CLK_IN)
begin
if (rising_edge(CLK_IN)) then
if (counter = 0) then
counter <= COUNTER_LOAD;
toggle <= not toggle;
CLK_OUT <= toggle;
else
counter <= counter - 1;
end if;
end if;
end process;
end CLOCK_DIV;