Experiment No.

07
Roll No. : 27

Aim :
Measurement of following timing characteristics of flip-flop. i) Propagation delay time. ii) Set up time , hold time. iii) Maximum clock frequency , pulse width.

Circuit Diagram:
O O D S O F F N T E L T A P P T I A R V M I M D E S = T M 2 .1 2 E C L =K 2 . 2 u Y = T V A L = 1 A L = 0

0
0 V R 1 1 k U 1 3
V

0
0 V R 1 1 A U 1 1 2 7 4 0 0 7 4 0 0
V

2 k

u s

s 2

A 3

O O D S O

F F N T E L T A P P

T I A R V

I M D E S =T M 2 2 s u E C L =K 2 u s Y = 4 . 9 T V A L = 0 A L = 1

0
V

1 9 6 U U U 1 7 4 5 2 0 4 0 7 4 0 0 A 1 3 2 1 7 4 0 0 2 4 A 1 3 3 A . 4 6 m V

Department of Electronics Engineering, YCCE, Nagpur 12/9/2011 3:09:39 a12/p12 Page 1 of 3

PSPICE Simulation Result :

Observed values:

T1 = 2.2us T2 = 4us T3 = 4.4us T4 = 6.6us

Calculations:

Set up time = T2-T1 = 4us-2.2us = 1.8us Hold time = T4-T2 = 6.6us-4us = 2.6us Propagation delay = T3-T2 = 4.4us-4us = 0.4us

Department of Electronics Engineering, YCCE, Nagpur 12/9/2011 3:09:39 a12/p12 Page 2 of 3

Result / Conclusion :

Set up time = 1.8us Hold time = 2.6us Propagation delay = 0.4us Thus we studied the timing characteristics of flip-flop.

Roll No. : Sem/Br :

Marks out of 10

Signature : Name of Lecturer :

Department of Electronics Engineering, YCCE, Nagpur 12/9/2011 3:09:39 a12/p12 Page 3 of 3