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HLNAND: A New Standard For High Performance Flash Memory: Peter Gillingham MOSAID Technologies Inc
HLNAND: A New Standard For High Performance Flash Memory: Peter Gillingham MOSAID Technologies Inc
Objectives
Address performance and density requirements of Solid State Drive (SSD) Cost effectively serve lower end applications
4 Key Flash Applications
SSD for HDD Replacement Flash Memory Card
1000
100 SSD High-end Flash Card for Prosumer 10 Generic Flash Memory Card & USB Driver Compressed Digital Video
Embedded Apps
HD Digital Video
MP3 1 4GB 8GB 16GB 32GB Density Santa Clara, CA USA August 2008 64GB 128GB 256GB
DRAM code storage low latency operation issue commands during data transfers multi-drop bus limited number of loads
Conventional NAND Flash high latency core long data transfers interrupt data transfer to issue commands multi-drop bus limited number of loads
HLNAND Flash high latency core long data transfers interrupt data transfer to issue commands point-to-point daisy chain unlimited number of loads
NAND
NAND
Controller
HLNAND 3 read 2
Santa Clara, CA USA August 2008
HLNAND 2
read 2
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HyperLink Advantages
Bandwidth
Point-to-point signaling extends to much higher data-rates than multi-drop bus
Power
No termination resistors required Point-to-point I/O drivers are much smaller than multi-drop bus drivers and have significantly lower capacitance Packet truncation at destination device reduces power
Scalability
Up to 255 devices in a single ring
Santa Clara, CA USA August 2008
HL1 Interface
DDR signaling up to 266MB/s, no PLL required No changes to existing Flash process
CSO DSO Q[7:0]
CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0] CSI DSI D[7:0] CSO DSO Q[7:0]
Controller
CK# CK CE# RST#
Q[7:0]
CSO DSO
Q[7:0]
CSO DSO
HL1 Timing
CSI/CSO Command and write data Strobe Input/Output DSI/DSO read Data Strobe Input/Output Data bursts can be interrupted by terminating CSI/DSI
tCK
tCKL
CK CK#
tT tCKH
CSI or DSI
tIS tIH
D0..w-1
tIH tIS
CSO or DSO
tOA tOH
Q0..w-1
tOH
w = current li nk width
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HL2 Interface
Source synchronous DDR to 800MB/s with on-chip PLL May require improvement to I/O transistor performance Fully backward compatible to HL1
CKO CKO# CSO DSO Q[7:0]
CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0] RST# CE# Vref CK CK# CSI DSI D[7:0] CKO CKO# CSO DSO Q[7:0]
Controller
Vref CE# RST#
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HLNAND Instructions
Operation Page Read Page Read for Copy Burst Data Read Burst Data Load Start Burst Data Load Page Program Block Erase Address Input Page-pair Erase Address Input Erase Operation Abort Read Status Register Read Device Information Register Read Link Configuration Register Write Link Configuration Register
Santa Clara, CA USA August 2008
1st Byte DA DA DA DA DA DA DA DA DA DA DA DA DA FF
2nd Byte 0Xh 1Xh 2Xh 4Xh 5Xh 6Xh 8Xh 9Xh AXh CXh Fyh F4h F7h FFh
3rd Byte RA RA CA CA CA RA RA RA
4th Byte RA RA CA CA CA RA RA RA
5th Byte RA RA
6th Byte
7th Byte
8th Byte
2116th Byte
DATA DATA
DATA DATA
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HLNAND Resources
Available at hlnand.com
Architectural Specification Datasheets White papers Technical papers Verilog Behavioral model
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4Gb (plane0)
4Gb (plane1)
4Gb (plane0)
4Gb (plane1)
4Gb (plane0)
4Gb (plane1)
4Gb (plane0)
4Gb (plane1)
4KB Page
4KB Page
4KB Page
4KB Page
4KB Page
4KB Page
4KB Page
4KB Page
X8 I/O
X8 I/O
X8 I/O
X8 I/O
Bank0
Bank1
Bank2
Bank3
HLNAND interface
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