Laptrinh VN KyThuatMIMO Va FPGA

Khoa in t Vin thng HCN - HQGHN
M U
K thut MIMO xut hin rt sm t nhng nm 70 do A.R Kaye v D.A
George ra nm 1970 v W. van Etten nm 1975, 1976. Trong qu trnh pht trin,
k thut ny khng ngng c ci tin. Vit Nam, do iu kin k thut cng ngh
cn kh xa vi th gii nn vic nghin cu cng gp nhiu kh khn, c bit l trong
qu trnh xy dng v test mt h MIMO. Tuy nhin, vi nm tr li y Vit Nam
bt u c tip cn vi mt cng ngh mi. l cng ngh FPGA. Vi cng
ngh ny th vic xy dng v test mt h MIMO khng cn qu xa vi.
Vi kin thc ca sinh vin nm cui khoa in t - vin thng em quyt
nh nhn mt ti kha lun lin quan n FPGA vi tn gi Thit k b pht m
Walsh cho h o knh MIMO dng cng ngh FPGA vi mc ch tng bc xy
dng mt h MIMO trong truyn thng v tuyn. Ni dung ca kha lun gm c 4
chng:
Chng 1: GII THIU V MIMO v FPGA. Trong chng ny em i vo
gii thiu v h MIMO v nhng nt chnh v FPGA nh khi nim v cu trc ca
FPGA.
Chng 2: NGN NG V MI TRNG LP TRNH CHO FPGA: gii
thiu khi qut v ngn ng lp trnh VHDL, Verilog v mi trng lp trnh cho
FPGA ca hng Xilinx l ISE.
Chng 3: CC C IM C BN CA KIT VIRTEX 4 V CC PHN
MM B TR gii thiu v kit FPGA Virtex 4 ca Xilinx cng c s dng trong
qu trnh nghin cu, thc hin ti v cc phn mm b tr nh MATLAB, FUSE,
cng c System Generator.
Chng 4: THC HIN M HNH THIT K VI KIT VIRTEX 4. Chng
ny a ra cch thc hin mt s thit k c th bng MATLAB cng cc cng c
sn c c cung cp bi Xilinx. Cui cng l kt qu thu c qua m phng v kt
qu quan st c trn giao ng k ti li ra ca thit k.
Kha lun tt nghip o Vn Qun K49B
1
CHNG 1: GII THIU V K THUT MIMO V FPGA
1.1. Gii thiu v MIMO
1.1.1. Khi nim
K thut MIMO (MIMO technique) trong lnh vc truyn thng l k thut s
dng nhiu anten pht v nhiu anten thu truyn d liu. K thut MIMO tn dng
s phn tp (khng gian, thi gian, m ha ...) nhm nng cao cht lng tn hiu, tc
d liu ... (khc vi khi nim beam forming ca smart aray antenna nhm nng
cao li thu, pht theo khng gian...). Tuy vy, hn ch ca k thut MIMO l chi
ph cho thit b cao hn v gii thut x l tn hiu phc tp hn.
K thut MIMO ngy nay ang c ng dng rt rng ri: MIMO-Wifi,
MIMO-UMTS ... nh tnh ti u trong vic s dng hiu qu bng thng, tc d d
liu cao, robust vi knh truyn fading ... K thut MIMO tng i a dng v phc
tp.
Hnh 1: M hnh mt h MIMO 4x4.
1.1.2. Lch s pht trin
K thut MIMO vi nhng u im y ca n ch mi xut hin cch y
khng lu, nhng nhng khi nim s khai v h MIMO xut hin rt sm t nhng
nm 70 do A.R Kaye v D.A George ra nm 1970, v W. van Etten nm 1975,
1976.
Gia thp nin tm mi, Jack Winters v Jack Salz lm vic ti Bell Labs
a ra nhng ng dng dng k thut to bp sng - c s dng trong h MIMO sau
ny.
Nm 1993, Arogyaswami Paulraj v Thomas Kailath xut khi nim hp knh
khng gian s dng h MIMO.
Nm 1996, Greg Raleigh v Gerard J.Foschini a ra phng php mi s dng
k thut MIMO da trn vic biu din dung nng nh hm ph thuc vo s anten thu
pht.
S/P
S1
S2
S3
S4
S4,S3,S2,S1
(Cc k hiu truyn)
2
Nm 1998, ln u tin trong lch s Bell Labs chng minh th nghim m hnh
hp knh khng gian (SM).
Nm 2001, sn phm thng mi u tin s dng cng ngh MIMO OFDMA
c a ra th trng bi hip hi Iospan Wireless Inc. Sn phm ny h tr c m
phn tp v hp knh khng gian.
Nm 2006, mt s cng ty vin thng ln (Beceem Communicatios, Samsung,
Runcom Technology ) tp trung pht trin k thut MIMO OFDMA lm gii php
cho chun di ng bng rng WIMAX IEEE 802.16e. Cng trong nm 2006 mt s
cng ty (Broadcom, Intel ) pht trin k thut MIMO OFDM chun b cho k thut
WiFi theo chun IEEE 802.11n.
Trong tng lai k thut MIMO vn cn rt quan trng trong h 4G, v vn ang
c nhiu nh nghin cu quan tm pht trin.
1.1.3. Phn loi
MIMO c th chia thnh 3 mng chnh: M trc (Precoding), hp knh khng
gian SM, v m phn tp.
M trc l cch to bp sng nhiu lp. Trong cch to bp sng n lp mi
anten pht s pht cc tn hiu ging nhau vi cc trng s pha thch hp cc i
cng sut ti u thu. Kt qu t to bp sng lm tng h s cng sut thng qua cu
trc tng hp, v lm gim hiu ng fading do a ng. Nu mi trng khng c
tn x th cch to bp sng ny rt c hiu qu. Nhng tht khng may nhng h
thng trong thc t u khng nh vy. Khi s dng nhiu anten nhn th bn pht
khng th to bp sng cc i tn hiu trn tt c cc anten nhn. Khi m trc
cn c s dng. Trong k thut ny, nhiu lung tn hiu c lp c pht ng
thi t cc anten pht vi cc trng s thch hp sao cho thng lng ti b thu cc
i. M trc yu cu bn pht phi bit thng tin trng thi knh (CSI).
Hp knh khng gian: yu cu cu hnh anten ph hp. Trong hp knh khng
gian, tn hiu tc cao c chia thnh nhiu lung tc thp hn, mi lung c
pht bi mt anten khc nhau trn cng mt bng tn. Nu cc lung tn hiu ny n
b thu c s khc bit k hiu khng gian thch hp th b thu c th tch bit cc
lung ny, to thnh cc knh song song. Hp knh khng gian rt hu hiu lm tng
dung nng ng k trong trng hp t s SNR cao. S lung khng gian cc i ng
bng hoc nh hn s anten nh nht bn pht v bn thu. Hp knh khng gian
khng yu cu bn pht phi bit knh.
M phn tp l k thut khi bn pht khng bit thng tin trng thi knh. Khng
nh k thut SM, m phn tp ch pht i mt lung tn hiu c m ho theo k thut
c gi l m khng thi gian. Cc anten pht tn hiu m ho trc giao. K thut
phn tp khai thc tnh c lp ca fading trong h nhiu anten nng cao s phn
tp ca tn hiu. V bn pht khng bit knh nn m phn tp khng to bp sng.
Trong thc t ngi ta c th kt hp k thut hp knh khng gian vi m trc
khi bn pht bit trng thi knh, hoc kt hp vi m phn tp trong trng hp
ngc li.
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1.1.4. ng dng ca MIMO
Li ch chnh ca h MIMO l tng ng k tc d liu v tin cy ca knh
truyn. K thut hp knh khng gian i hi phc tp ca b thu, do n thng
c kt hp vi k thut hp knh phn chia theo tn s trc giao (OFDM), hoc
OFDMA. Chun IEEE 802.16e kt hp cht ch vi k thut MIMO OFDMA v
chun IEEE 802.11n s dng MIMO OFDM.
H MIMO cng c s dng trong chun di ng 3GPP v 3GPP2 v ang
c pht trin k thut truyn thng MIMO nng cao nh l k thut xuyn lp, k
thut nhiu ngi dng v ad hoc trong MIMO.
Xuyn lp MIMO gii quyt cc vn xuyn lp xy ra trong h thng MIMO,
do lm tng hiu qu s dng knh. K thut xuyn lp ny cng lm tng hiu qu
s dng knh SISO. Cc k thut xuyn lp thng gp l iu ch v m ho thch
nghi (AMC), lin kt thch nghi.
MIMO nhiu ngi dng c th khai thc s giao thoa cng sut ca nhiu ngi
s dng nh l mt ti nguyn khng gian cho k thut x l pht tin tin, cn trong
ch mt ngi dng, h MIMO ch s dng nhiu anten. V d cho x l pht tin
tin ca h MIMO nhiu ngi dng l giao thoa lin quan n m trc.
Ad hoc MIMO l mt k thut rt hu dng cho mng t bo tng lai, n tp
trung vo mng v tuyn mt co hay mng v tuyn ad hoc. Trong mng ad hoc
nhiu nt pht lin lc vi nhiu nt thu. c th ti u dung nng ca knh Ad
hoc, khi nim v k thut MIMO c p dng cho cc lin kt trong cm nt thu v
pht. Khng ging vi h anten trong h MIMO mt ngi dng, cc nt ny c t
nh mt hng phn b. t c dung nng trong mng ny cn qun l s phn b
ti nguyn sng v tuyn hiu qu nh s hot ng ng thi ca cc nt v khi
nim m trang nhim bn.
Tm li, h MIMO vi nhng k thut phn tp, m trc v nhiu ngi dng
lm tng ng k tc d liu v tin cy knh truyn, ang rt c quan tm
nghin cu pht trin ha hn m li cho chng ta nhiu li ch hn na trong truyn
thng v tuyn.
1.2. Gii thiu v FPGA
1.2.1. Khi nim
Field-programmable gate array (FPGA) l vi mch dng cu trc mng phn
t logic m ngi dng c th lp trnh c. (Ch field y mun ch n kh nng
ti lp trnh bn ngoi ca ngi s dng, khng ph thuc vo dy chuyn sn xut
phc tp ca nh my bn dn). Vi mch FPGA c cu thnh t cc b phn (hnh
2):
Cc khi logic c bn lp trnh c (logic block).
H thng mch lin kt lp trnh c.
Khi vo/ra (I/O Pads).
Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...
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Hnh 2: Cu trc c bn ca FPGA
FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng
nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin
logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong
kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit hn ch
c th ti cu trc li khi ang s dng, cng on thit k n gin do vy chi ph
gim, rt ngn thi gian a sn phm vo s dng.
Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc
mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v ti
lp trnh ca FPGA thc hin n gin hn; kh nng lp trnh linh ng hn; v khc
bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha khi lng
ln cng logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n.
Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m
t phn cng HDL nh VHDL, Verilog, AHDL, cc hng sn xut FPGA ln nh
Xilinx, Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnh
thit k, cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny nh
Synopsys, Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bc
ca ton b quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi l
m RTL).
FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty Xilinx
vo nm 1984, kin trc mi ca FPGA cho php tnh hp s lng tng i ln cc
phn t bn dn vo mt vi mch so vi kin trc trc l CPLD. FPGA c kh
nng cha ti t 100.000 n hng vi t cng logic, trong khi CPLD ch cha t
10.000 n 100.000 cng logic; con s ny i vi PAL, PLA cn thp hn na ch
t vi nghn n 10.000.
CPLD c cu trc t s lng nht nh cc khi SPLD (Simple programable
devices, thut ng chung ch chung ch PAL, PLA). SPLD thng l mt mng logic
AND/OR lp trnh c c kch thc xc nh v cha mt s lng hn ch cc
phn t nh ng b (clocked register). Cu trc ny hn ch kh nng thc hin
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nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph thuc vo
cu trc c th ca vi mch hn l vo yu cu bi ton.
Kin trc ca FPGA l kin trc mng cc khi logic, khi logic, nh hn nhiu
nu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha nhiu hn
cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t logic v h
thng mch kt ni, t c mc ch ny th kin trc ca FPGA phc tp hn
nhiu so vi CPLD.
Mt im khc bit vi CPLD l trong nhng FPGA hin i c tch hp
nhiu nhng b logic s hc s b ti u ha, h tr RAM, ROM, tc cao, hay
cc b nhn cng (multication and accumulation, MAC), thut ng ting Anh l DSP
slice dng cho nhng ng dng x l tn hiu s DSP.
Ngoi kh nng ti cu trc vi mch ton cc, mt s FPGA hin i cn h tr
ti cu trc cc b, tc l kh nng ti cu trc mt b phn ring l trong khi vn m
bo hot ng bnh thng cho cc b phn khc.
1.2.2. ng dng
ng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng khng,
v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), cc h thng iu
khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m hc, m hnh
phn cng my tnh...
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp
nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi ra
nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi
lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.
Khi logic
Phn t chnh ca FPGA l cc khi logic (logic blocks). Khi logic c cu
thnh t LUT v mt phn t nh ng b flip-flop, LUT (Look up table) l khi logic
c th thc hin bt k hm logic no t 4 u vo, kt qu ca hm ny ty vo mc
ch m gi ra ngoi khi logic trc tip hay thng qua phn t nh flip-flop.
Hnh 3: Khi logic trong FPGA
Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi nim
SLICE, mt Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t vi
nghn n vi chc nghn ty theo loi FPGA.
Look Up
Table
(LUT)
Flip-
Flop
Input
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Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h tr
thm 2 u vo b xung t cc khi logic phn b trc v sau n nng tng s u
vo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic.
1.2.3. H thng mch lin kt
Khi chuyn mch ca FPGA l mng lin kt trong FPGA c cu thnh t
cc ng kt ni theo hai phng ngang v ng, ty theo tng loi FPGA m cc
ng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c
3 loi kt ni: ngn, di v rt di. Cc ng kt ni c ni vi nhau thng qua cc
khi chuyn mch lp trnh c (programable switch), trong mt khi chuyn mch
cha mt s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tp
khc nhau.
1.2.4. Cc phn t tch hp sn
Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch
hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5 ca
Xilinx c cha nhn s l PowerPC, hay trong Atmel FPSLIC tch hp nhn ARV,
hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp cc DSP
Slice l b nhn cng tc cao, thc hin hm A*B+C, v d dng Virtex ca Xilinx
cha t vi chc n hng trm DSP slices vi A, B, C 18-bit.
Ngy nay ngnh cng ngh ch to phn cng lun c nhng t ph khng
ngng. T cc mch in n gin n cc mch s, mch tch hp, kin trc mch
tr nn ngy mt phc tp hn. Nh nhng u im hn hn so vi cc phng php
phn tch, m hnh ho, thit k mch s kiu truyn thng m phng php s
dng cc ngn ng m phng phn cng (HDL - Hardware Description Languages)
ang tr thnh mt phng php thit k cc h thng in t s ph bin trn ton
th gii. Trong kha lun ny em xin gii thiu hai loi ngn ng m phng phn cng
l VHDL (Very high speed intergrated circuit Hardware Description Language) v
Verilog l hai ngn ng ch yu c s dng m phng phn cng trong cng
ngh CPLD, FPGA, ASIC
Nhng u im ca phng php thit k h thng s bng ngn ng
m phng phn cng (HDL).
Ngy nay, cc mch tch hp ngy cng thc hin c nhiu chc nng do
m vn thit k mch cng tr nn phc tp. Nhng phng php truyn thng
nh dng phng php ti thiu ho hm Boolean hay dng s cc phn t khng
cn p ng c cc yu cu t ra khi thit k. Nhc im ln nht ca cc
phng php ny l chng ch m t c h thng di dng mng ni cc phn t
vi nhau. Ngi thit k cn phi i qua hai bc thc hin hon ton th cng:
l chuyn t cc yu cu v chc nng ca h thng sang biu din theo dng hm
Boolean, sau cc bc ti thiu ho hm ny ta li phi chuyn t hm Boolean sang
s mch ca h thng. Cng tng t khi phn tch mt h thng ngi phn
tch cn phi phn tch s mch ca h thng, ri chuyn n thnh cc hm
Boolean, sau mi lp li cc chc nng, hot ng ca h thng. Tt c cc bc
ni trn hon ton phi thc hin th cng khng c bt k s tr gip no ca my
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tnh. Ngi thit k ch c th s dng my tnh lm cng c h tr trong vic v s
mch ca h thng v chuyn t s mch sang cng c tng hp mch vt l
dng cng c Synthesis. Mt nhc im khc na ca phng php thit k truyn
thng l s gii hn v phc tp ca h thng c thit k. Phng php dng
hm Boolean ch c th dng thit k h thng ln nht biu din bi vi trm hm.
Cn phng php da trn s ch c th dng thit k h thng ln nht cha
khong vi nghn phn t.
Phng php thit k, th nghim, phn tch cc h thng s s dng cc ngn
ng m t phn cng ni bt ln vi cc u im hn hn v s dn thay th cc
phng php truyn thng. S ra i ca ngn ng m phng phn cng gii quyt
c rt nhiu nhc im ln ca cc phng php thit k trc y: Nu cc
phng php c i hi phi chuyn i t m t h thng (cc ch tiu v chc
nng) sang tp hp cc hm logic bng tay th bc chuyn hon ton khng cn
thit khi dng HDL. Hu ht cc cng c thit k dng ngn ng m phng phn
cng u cho php s dng biu trng thi (finite-state-machine) cho cc h thng
tun t cng nh cho php s dng bng chn l cho h thng tng hp. Vic
chuyn i t cc biu trng thi v bng chn l sang m ngn ng m phng
phn cng c thc hin hon ton t ng.
Nh tnh d kim tra th nghim h thng trong sut qu trnh thit k m
ngi thit k c th d dng pht hin cc li thit k ngay t nhng giai on u,
giai on cha a vo sn xut th, do tit kim c lng chi ph ng k bi
t t ng thit k n to ra sn phm ng nh mong mun l mt vic rt kh
trnh khi nhng kh khn, tht bi.
Khi mi lnh vc ca khoa hc u pht trin khng ngng th s phc tp ca
h thng in t cng ngy mt tng theo v gn nh khng th tin hnh thit k th
cng m khng c s tr gip cu cc loi my tnh hin i. Ngy nay, ngn ng
m t phn cng HDL c dng nhiu thit k cho cc thit b logic lp trnh
c PLD t loi n gin n cc loi phc tp nh ma trn cng lp trnh c
FPGA.
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CHNG 2: NGN NG V MI TRNG LP TRNH CHO FPGA
2.1. Ngn ng lp trnh cho FPGA
2.1.1 Gii thiu
C nhiu ngn ng c th lp trnh cho FPGA nh VHDL, Verilog, C Mi
ngn ng li c u nhc im ring. V d nh Verilog l ngn ng c pht trin
v s dng ch yu M. y l mt ngn ng rt gn vi C, chnh v vy s rt
thun tin cho ai quen lp trnh vi ngn ng C. Tuy nhin, chu u th ngi
ta li quen dng VHDL hn. u im ca ngn ng ny l ngi lm vic vi n s
c ci nhn rt thu o v phn cng. Trong chng ny em xin c gii thiu ch
yu v v ngn ng VHDL ngn ng m em tm hiu trong qu trnh hc tp v
lm thc nghim vi FPGA trn phng SIS (Smart Integrated Systems) v a ra vi
nt gii thiu khi qut v Verilog cng l mt ngn ng rt thng dng i vi lp
trnh FPGA hin nay.
2.1.2. Ngn ng VHDL
2.1.2.1. Khi nim
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt
loi ngn ng m t phn cng c pht trin dng cho chng trnh VHSIC (Very
High Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin
VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho
php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h
thng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics,
IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm 1983. Phin
bn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chc
IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL
(tiu chun IEEE-1076-1987).
VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i
v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu
m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu k lng ti
liu . Vi mt ngn ng m phng phn cng tt vic xem xt cc ti liu m t
tr nn d dng hn v b ti liu c th c thc thi m phng hot ng ca
h thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trong
mt m hnh thng nht.
VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt
phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k
c th t do la chn cng ngh, phng php thit k trong khi ch s dng mt
ngn ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc
k ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc:
- Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh
ph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh
sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng.
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- Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL
cho php thit k bng nhiu phng php v d phng php thit k t trn xung,
hay t di ln da vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng c
xy dng mch nh s dng cng ngh ng b hay khng ng b, s dng ma trn
lp trnh c hay s dng mng ngu nhin.
- Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh
ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c
chuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch to phn
cng mi ra i n c th c p dng ngay cho cc h thng thit k.
- Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phn
cng t mc h thng s cho n mc cng. VHDL c kh nng m t hot ng ca
h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi
mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t
chi tit.
- Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chp
nhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu chun
VHDL. Cc kt qu m t h thng c th c trao i gia cc nh thit k s dng
cng c thit k khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mt
nhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thng
ln (trong cc h con c thit k c lp).
- Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thit
k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th c
s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bn
trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s
thit k. V n cng cho php dng li cc phn c sn.
2.1.2.2. Cu trc mt m hnh h thng m t bng VHDL
Mc ch ca phn ny l nhm gii thiu s qua v cu trc khung c bn ca
VHDL khi m t cho mt m hnh thit k thc. Thng thng mt m hnh VHDL
bao gm ba phn: thc th (entity), kin trc (architecture) v cc cu hnh. i khi ta
s dng cc gi (packages) v m hnh kim tra hot ng ca h thng (testbench).
+ Thc th (entity)
y l ni cha cc khai bo thc th (l cc port giao tip gia FPGA v cc tn
hiu bn ngoi cc port ny c s dng nh l lp v ca kin trc thit k) v c
th bao gm cc ty chn generic l khai bo chung c th d dng sa i khi cn.
+ Kin trc (architecture)
Phn th hai trong m hnh VHDL l khai bo kin trc ca chng trnh. Mi
mt khai bo thc th u phi i km vi t nht mt kin trc tng ng. VHDL
cho php to ra hn mt kin trc cho mt thc th. Phn khai bo kin trc c th
bao gm cc khai bo v cc tn hiu bn trong, cc phn t bn trong h thng, hay
cc hm v th tc m t hot ng ca h thng. Tn ca kin trc l nhn c
t tu theo ngi x dng. C hai cch m t kin trc ca mt phn t (hoc h
thng) l m hnh hot ng (Behaviour) hay m t theo m hnh cu trc
(Structure). Tuy nhin mt h thng c th bao gm c m t theo m hnh hot ng
10
v m t theo m hnh cu trc.
+ M t kin trc theo m hnh hot ng
M hnh hot ng m t cc hot ng ca h thng (h thng p ng vi cc
tn hiu vo nh th no v a ra kt qu g u ra) di dng cc cu trc ngn
ng lp trnh bc cao. Cu trc c th l PROCESS, WAIT, IF, CASE, FOR-
LOOP
+ M t kin trc theo m hnh cu trc
M hnh cu trc ca mt phn t (hoc h thng) c th bao gm nhiu cp
cu trc bt u t mt cng logic n gin n xy dng m t cho mt h thng
hon thin. Thc cht ca vic m t theo m hnh cu trc l m t cc phn t con
bn trong h thng v s kt ni ca cc phn t con . Nh vi v d m t m
hnh cu trc mt flip-flop RS gm hai cng NAND c th m t cng NAND c
nh ngha tng t nh v d vi cng NOT, sau m t s mc ni cc phn t
NAND to thnh trig RS.
+ Cu trc process
Process l khi c bn ca vic m t theo hot ng. Process c
xt n nh l mt chui cc hnh ng n trong sut qu trnh dch.
Hnh 4: Cu trc process
S: M hnh cu trc
B: M hnh hot ng
S/B: M hnh kt hp
Cu trc tng qut
[Process label]
Process [(sensitive_list )]
Process declarative part
Begin
S
S
B
S S/B S
B B B B B B
11
.
End process
Trong cc phn t trong du [ ] th c th c hoc khng.
- process_label: (nhn lnh) l tu thuc ngi lp trnh t tn
- sensitivity_list: Danh sch cc yu t kch thch hot ng.
+ Mi trng kim tra (testbench)
Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tra
mt m hnh VHDL c thc hin bng cch quan st hot ng ca n trong khi
m phng v cc gi tr thu c c th em so snh vi yu cu thit k.
Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kim
tra sinh ra cc tc ng ln bn thit k v cho php quan st hoc so snh kt qu
hot ng ca bn m t thit k. Thng thng th cc bn m t u cung cp
chng trnh th. Nhng ta cng c th t xy dng chng trnh th (testbench).
Mch th thc cht l s kt hp ca tng hp nhiu thnh phn. N gm ba thnh
phn. M hnh VHDL qua kim tra, ngun d liu v b quan st. Hot ng ca
m hnh VHDL c kch thch bi cc ngun d liu v kim tra tnh ng n
thng qua b quan st.
Hnh 5: S khi ca Testbench
Trong : DUT: (device under test) m hnh VHDL cn kim tra.
Observer: khi quan st kt qu.
Data source: ngun d liu (khi to ra cc tn hiu kch thch).
2.1.3. Gii thiu khi qut v ngn ng Verilog
Verilog HDL l mt trong hai ngn ng m phng phn cng thng dng nht
cng vi VHDL c dng trong thit k IC. Verilog HDL cho php m phng cc
thit k d dng, sa cha li, hoc thc nghim bng nhng cu trc khc nhau. Cc
thit k c m t trong Verilog HDL l nhng k thut c lp, d thit k, d tho
g v thng d c hn dng biu , c bit l cc mch in ln.
Verilog thng c dng m t thit k bn dng
Data Source
(stimuli
Generator)
Observer DUT
Generics
Testbench Entity
12
Thut ton (mt s lnh ging ngn ng C nh: if, case, for,while).
Chuyn i thanh ghi (kt ni bng cc biu thc Boolean).
Cc cng kt ni (cng: OR, AND, NOT).
Chuyn mch (BJT, MOSFET).
Ngn ng ny cng ch r cch thc kt ni, iu khin vo/ra trong m phng.
Khai bo module
Mt module l bn thit k ch yu tn ti trong Verilog. Dng u tin ca khai
bo module ch r danh sch tn v port (cc i s). Nhng dng k tip ch r dng
I/O (input, output, hoc inout) v chiu rng ca mi port. Mc nh chiu rng port l
1 bit.
Sau , nhng bin port phi c khai bo wire, wand, , reg. Mc nh l
wire. Nhng ng vo c trng l wire khi d liu c cht bean ngoi module. Cc
ng ra l dng reg nu nhng tn hiu ca chng c cha trong khi always hoc
initial.
Ch th lin tip
Cc ch nh lin tip c dng gn mt gi tr ln trn mt wire trong mt
module. l cc ch nh thng thng bn ngoi khi always hoc khi initial. Cc
ch nh lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s ch
nh mt gi tr n mt wire trong lc khai bo. Ch rng, cc lnh ch nh lin
tip th tn ti v c chy lin tc trong sut qu trnh m phng. Th t cc lnh
gn khng quan trng. Mi thay i bn phi ca bt c ng vo s lp tc thay i
bn tri ca cc ng ra.
Module instantiations
Nhng khai bo module l nhng khun mu m n c to nn t cc i
tng thc t (instantiation). Cc module n c bn trong cc module khc, v mi
dn chng to mt i tng c nht t khun mu. Ngoi tr l module mc trn
l nhng dn chng t chnh chng. Cc port ca module v d phi tha nhng nh
ngha trong khun mu. y l mt l thuyt: bng tn, s dng du chm (.) .tn
port khun mu (tn ca wire kt ni n port). Bng v tr, t nhng port nhng v
tr ging nhau trong danh sch port ca c khun mu ln instance.
BEHAVIORAL
Verilog c 4 mc khun mu:
Chuyn mch.
Cng.
Mc trn d liu.
Hnh vi hoc th tc c cp bn di.
Cc lnh th tc Verilog c dng to mt mu thit k mc cao hn. Chng ch ra
nhng cch thc mnh ca vc lm ra nhng thit k phc tp. Tuy nhin, nhng thay
13
i nh n phng php m ha c th gy ra bin i ln trong phn cng. Cc lnh
th tc ch c th c dng trong nhng th tc.
Nhng ch nh theo th tc:
L nhng ch nh dng trong phm vi th tc Verilog (khi always v initial). Ch
bin reg v integers (hoc chn n bit/ nhm bit ca chng hoc kt ni thng tin) c
th c t bn tri du = trong th tc. Bn phi ca ch nh l mt biu thc m
c th dng bt c dng ton t no.
Delay trong ch nh:
Trong ch nh tr t l khong thi gian tri qua trc khi mt lnh c thc thi v
bn tri lnh gn c to ra. Vi nhiu ch nh tr (intra-assignment delay), bn phi
c nh gi tr trc tip nhng c mt delay ca t trc khi kt qu c t bn
tri lnh gn. Nu thm mt qu trnh thay i na cnh bn phi tn hiu trong
khong thi gian t, th khng cho kt qu ng ra. Delay khng c h tr bi cc
cng c.
Cu trc chng trnh dng ngn ng Verilog
// Khai bo module
Module tn chng trnh (tn bin I/O); // tn chng trnh trng tn file.v.
Input [msb:lsb] bin;
Output [msb:lsb] bin;
Reg [msb:lsb] bin reg;
Wire [msb: lsb] bin wire;
// Khai bo khi always, hoc khi initial.
cc lnh
2.2. Mi trng lp trnh cho FPGA
Hin nay, c nhiu nh cung cp sn phm FPGA trn th trng nh Altera,
Xilinx, Actel Sn phm ca mi nh cung cp li c nhng u, nhc im ring do
cc hng u sn xut theo cng ngh ring ca mnh. Chnh v vy mi hng li a
ra mt sn phm phn mm ring i km lm mi trng thit k v np cho chip
FPGA ca hng nh ca Altera l Quartus II, Actel c Actel Libero cn Xilinx c
ISE. Trong kha lun ny em ch xin gii thiu v ISE phn mm h tr cho Kit
Virtex 4 ca Xilinx m em s dng thc hin kha lun ny.
2.2.1. ISE
H thng phn mm ISE ca Xilinx l mt mi trng thit k tch hp bao gm
thit k chng trnh, m phng v thc hin cc thit k trn cc thit b FPGA hay
CPLD. ISE c th tham gia vo vic iu khin mi giai on trong quy trnh thit
k.Thng qua giao din ca ISE, ngi dng c th can thip vo cc thit k v s
14
dng cc cng c thc hin thit k. Ngoi ra ngi dng cn c th can thip vo cc
file hay ti liu c lin quan n project ang thit k.
Giao din phn mm ISE
Hnh 6: Giao din phn mm ISE
Ca s ngun
Ca s ny bao gm cc file ngun ca 1 project (gm cc file c vit hoc
cc file c sn c a vo project). Trong ca s ny c mt danh sch m qua
ngi dng c th chn cc file ngun cho cc mc ch thit k c th nh tng hp,
thc thi hay m phng.
Ca s x l
Ca s ny cho ta bit cc thit k sn sng chy (bao gm c m phng
v thc thi) hay cha (v d khi bn mun chy mt thit k trong file ngun chn).
chy mt thit k, ta click p vo thit k , khi thit k c thc thi thnh
cng, mt du tch xanh s xut hin bn cnh thit k . Khi chy mt thit k, ISE
s t ng chy cc thit k nh h tr cho thit k .
2.2.2. Cc bc to ra mt thit k vi ISE
2.2.2.1. To mt Project
Chn File > New Projectxut hin thut s to Project mi.
G tn Project trong trng Project Name field.
Chn n th mc mun cha Project ri chn Next.
Ch rng HDL phi c la chn t danh sch Top-Level Source Type, cc
thng s khc chn nh trong hnh 7.
15
Hnh 7: Cc la chn to project vi Virtex 4.
2.2.2.2. To m ngun VHDL
to ra file m ngun VHDL cho Project ta lm nh sau:
Chn New Source trong New Project Wizard.
Chn kiu m ngun VHDL Module.
G t bn phm tn ca file m ngun l counter (v d l to ra m ngun cho
counter).
Quan st thy rng h kim tra Add to project c la chn.
Kch Next.
Khai bo cc cng cho b counter bng cch in cc thng tin nh hnh di
y:
Hnh 8: Khai bo cc cng cho mt v d to mt counter 4 bit.
Kich Next cho ti khi kt thc v mt file VHDL c to ra vi cc khai bo
ban u l cc cng in, out
16
T y ta c th vit m ngun VHDL cho b counter nhng ta cng c th ly
counter trong v d c sn ca ISE. s dng v d ny ta lm nh sau:
M v d bng cch: Edit > Language Template
Dng biu tng + duyt n m ngun ca v d nh sau: VHDL >
Synthesis Constructs >Coding Examples>Counters>Binary>Up/Down Couter>Simple
Counter.
dng la chn Simple Counter ta chn Edit > Use in File hoc chn nt Use
Template in File trn Toolbar.
ng ca s Language Template.
Nh vy m VHDL trong v d c chn vo file m ngun m ta mun to.
chng trnh ny c th chy ng c ta phi quan st v sa li mt s
ch cho ph hp vi khai bo ban u. l nhng v tr m chng trnh nh du
trong du <...> cui cng ta c file m ngun c ni dung nh sau:
entity counter is
Port ( Clock : in STD_LOGIC;
Direction : in STD_LOGIC;
c : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
begin
process (Clock)
begin
if Clock='1' and Clock'event then
if Direction ='1' then
c <= c + 1;
else
c <= c - 1;
end if;
end if;
end process;
end Behavioral;
2.2.2.3. M phng
Ta c th dng chc nng m phng ca ISE kim tra chc nng ca thit k va
c to ra:
To dng sng mun kim tra ta lm nh sau:
17
Chn file Counter t ca s Source.
To mt test bench t Project > New Source.
Trong ca s New Source Wizard chn Test Bench WaveForm v g t bn phm
counter_tbw trong trng tn file ri kick Next cho n khi xut hin ca s:
Hnh 9: Thit lp cc tham s m phng.
t cc thng s nh hnh 9 v kch Finish:
chy m phng ta thit lp cc thng s nh khong thi gian m tin, thi gian
m li bng cch kch chut vo v tr m ta mun cho kt thc m tin khi dng
xung bt u t s v tr logic 0 v bt u m li. Ta c th ty chn cc khong
m tin hoc li theo mun.
Hnh 10: Thit lp thi gian m tin, li cho counter.
Sau ng ca s ny li v chuyn sang bc m phng.
M phng
Ti ca s Source ta chn Behavioral Simulation v chn counter_tbw.
18
Ti ca s Process ta kch chut vo du + ri kch p vo Generate Expected
Simulation Results thc hin m phng. Ta c kt qu nh sau:
Hnh 11: Kt qu m phng ca counter.
2.2.2.4. To rng buc thi gian
Bc ny s to ra rng buc v thi gian, l thi gian m ta rng buc khi chy
trong FPGA.
Chn Synthesis/Implementatorn.
Chn file ngun counter HDL.
Kch vo du + User Constraints v chn Create Timing Constraints.
Sau bc ny s to ra cho bn file.UCF v ta c th thit lp cc thng s theo
tnh ton m thit k s phi p ng.
2.2.2.5. Gn chn
Chn file ngun l counter trn ca s Source.
Chn Assign Package Pins trong ca s Process.
T y ta c th gn chn c th a thit k vo phn cng tht. Ty tng
dng c th m ta t chn cn c vo bng chn c cung cp bi nh sn xut.
Kt thc bc ny ta c th a thit k vo phn cng v quan st trn cc li vo ra
ca phn cng bng nhng thit b h tr quan st nh giao ng k hay n LED.
19
CHNG 3: CC C IM C BN CA VIRTEX 4 V CC PHN
MM H TR
3.1. Nhng c im c bn ca XtremeDSP Development Kit Pro (Virtex IV)
3.1.1. Gii thiu chung
L cng ty u tin nghin cu ra FPGA, Xilinx lun l mt hng i u trong
vic nghin cu v cho ra nhng dng sn phm h tr cho gio dc cng nh cc b
Kit chuyn dng s dng trong nhiu ng dng c th. The XtremeDSP Development
Kit l b Kit c kh nng cung cp mt nn tng pht trin cao cho Cng Ngh FPGA.
y l mt cng c rt mnh c s dng trong nhiu ng dng c bit l cc ng
dng v DSP. Virtex 4 c hai b ADC v hai b DAC vi phn gii l 14 bit vi
tc xung nhp cao cho php ngi dng c th lp trnh v x l cho nhiu ng
dng khng ch ring trong DSP nh cc ng dng Software Defined Radio, 3G
Wireless, Networking, HDTV hoc hnh nh Video. B KIT c cha mt bo mch ch
ni vi mt module nm trn mt board mu xanh. Bo mch ch c gi l
BenONE-Kit Motherboard v module trn c gi l BenADDA DIME-II module.
BenONE-Kit l mt dng gn ln cc module h tr cho cc tnh nng khc.
Di y l mt s h tr ca BenONE-Kit:
H tr cho module BenADDA DIME-II.
H tr giao din USB hoc 3.3V/5V PCI.
H tr giao din PCI 3.3V/5V 32 bit/33-MHz v giao din USB 1.1.
Cc LED hin th.
Mch to cu hnh JTAG.
Cc chn cm ni trc tip vi ngi dng c th lp trnh c (FPGA I/O).
Module BenADDA DIME-II.
Chp FPGA: XC4VSX35-10FF668.
Hai knh DAC c lp: AD6645 ADC (14-bits 105 MSPS).
Hai knh ADC c lp: AD9772 DAC (14-bits 160MSPS).
H tr clock ngoi, b dao ng onboard v clock c th lp trnh.
Hai b nh SRAM (133MHz, 512Kx32 bits mi bn).
Cc LED hin th.
Di y l mt s hnh nh m t v Kit Virtex 4.
20
Hnh 12: Giao din ngoi ca XtremeDSP Development Kit Pro.
Hnh 13: Giao din pha trong v cc thnh phn ca Virtex IV Pro.
3.1.2. Cc thnh phn chnh ca Virtex 4
Chp FPGA (XC4VSX35-10FF668)
Cc c im chnh ca XC4VSX35-10FF668:
- Rocket IO Transceiver Blocks: 8
- PowerPC Processor Blocks: 2
- LogicCells: 30,816
- Slices: 13,696
- Max DistrRAM (Kb): 428
- 18 X 18 Bit Multiplier Blocks: 136
- 18 Kb Blocks: 136
- Max Block RAM (Kb): 2,448
- DCMs: 8
- Maximum User I/ O Pads: 644
21
Cc b ADC
Module BenADDA DIME-II s dng trong XtremeDSP Development Kit Pro
c hai knh vo tng t, mi knh c d liu v tn hiu iu khin c lp ti
FPGA.Hai ADC (AD6645) cho php thc hin hai thit lp d liu vi rng 14 bit.
Tn hiu a vo ADC v tn hiu ra thng qua chun kt ni MCX. S khi th
hin kt ni gia cc b ADC c th hin nh hnh 14. Vi kit Virtex 4 hay mt s
dng kit ca Xilinx c h tr XC2V80-4CS114 c nhim v iu khin xung Clock
cho ADC. Nh vy, ta c th la chn c tc ly mu ph hp vi yu cu thit
k vi tng bi ton c th.
Hnh 14: S tn hiu qua ADC vo FPGA.
Cc c im chnh ca khi ADC (AD6645)
Cung cp ADC 14-bit, kiu m b 2.
Tc ly mu 105MSPS.
Tr khng vo 50 cho tn hiu t l hay li vo thay i vi phn.
B lc bc 3 li vo.
Clock ADC c th thay i c.
Hnh 15: S khi ca b ADC (AD6645).
22
ADC clock
Mi ADC c th c thit lp clock trc tip bng tn hiu LVPECL mt cch
c lp. Tn hiu LVPECL c th c iu khin bng Virtex-II XC2V80-4CS144
FPGA (Clock FPGA). Mt s cc clock c th dng trong FPGA:
- Clock 105 MHZ on board bng tinh th.
- Clock ngoi a vo thng qua chun kt ni MCX.
- Clock lp trnh qua b dao ng trn KIT.
Ch rng b ADC (AD6645) ch c th h tr clock vo ln nht ln ti 105
MHZ. iu ny rt quan trng nu mun s dng mt trong cc clock DIME (V d
nh CLKA, CLKB, CLKC), v nhng clock c th ln hn 105 MHz.
Hnh 16: S ca ADC clock.
Cc b DAC (AD9772A)
Module BenADDA DIME-II s dng trong XtremeDSP Development Kit Pro c
hai knh li ra tng t, mi knh c d liu v tn hiu iu khin c lp ti FPGA.
Hai b DAC (AD9772A) cung cp hai ng d liu mi ng 14 bit. Tn hiu vo
v tn hiu ra thng qua kt qa kt ni MCX.
Hnh 17: S giao tip b DAC vi GPGA.
23
Cc c im chnh ca DAC (AD9772A)
Cung cp DAC 14-bit.
Tc d liu li ra ti a 160MSPS.
S dng clock LVPECL li vo ly t XC2V80-4CS144 Clock FPGA.
B nhn ng h c vng kha pha trong.
Tr khng li ra 50 thng qua chun kt ni MCX.
Hnh 18: S khi tip b DAC.
DAC clock
Mi DAC c th c clock trc tip, c lp thng qua tn hiu LVPECL. Tn
hiu LVPECL c th c iu khin bi Virtex-II XC2V80-4CS144 FPGA (Clock
FPGA). Mt s cc clock c th s dng thng qua clock FPGA:
- Clock 105 MHZ on board bng tinh th.
- Clock ngoi a vo thng qua chun kt ni MCX.
- Clock lp trnh qua b dao ng trn KIT.
B nh ZBT SRAM
B KIT cung cp 2 b nh c lp ZBT SRAM. Mi b c th cu hnh 512k x
32. B nh ny c kh nng lu d liu trn board thng qua bus d liu 32-bit ti mi
b nh.
c im chnh ca ZBT SRAM
Thi gian chu k nhanh: 6ns, 7.5ns v 10ns.
100% bus c tn dng.
iu khin qua giao din tn hiu ti thiu.
C cc chn iu khin c/vit ring.
S dng tn hiu iu khin, a ch thanh ghi, d liu vo ra, c th thit lp
c clock.
24
Cho php d liu vo ra thng thng.
C mode tuyn tnh hoc ghp xen.
Hnh 19: S ZBT SRAM.
ZBT SRAM Clocking
Hai b nh ZBT SRAM trn b KIT c th c g nhp c lp thng qua vic
chn thm tn hiu xung nhp phn hi. Mi b nh c mt tn hiu c th c hiu
chnh trong FPGA m bo cho xung nhp gia ZBT SRAM v chn phn hi c xung
nhp cng nhau vi sai khc nh nht. Qu trnh ny m bo cho logic trong c
kha pha vi d liu a vo.
Bng1: K hiu chn ca ZBT SRAM clocking.
Vo ra s
Mt s c im vo ra ca b KIT:
Mt u bus 14 chn trn bo mch ch. N cho php 12 kt ni trc tip hai
chiu ti FPGA vi hai chn ni t.
Mt u bus 34 chn hiu chnh trn bo mch ch. N cho php 28 kt ni trc
tip hai chiu ti chip FPGA. Cc phn cn li cho cc kt ni 3,3V, ni t v 'khng
c ni'.
Hai u vo ra 2 chn cung cp 2 kt ni hai chiu ti chip FPGA.
25
Clock
B KIT XtremeDSP Development Kit c mt h thng qun l clock ton din
v linh hot. Sau y l mt s c im ca h thng clock:
- B KIT c mt ngun pht tinh th 105 MHz trn module chnh cung cp clock
cho cc thit b tng t.
- Mt li vo cho clock ngoi trn bo mch ch c th thit lp c tn s
- Mt khe cm cho b dao ng trn bo mch ch. Ch rng trn bo mch ch
khng c b dao ng m ch c socket ngi dng s dng cc b dao ng cho
cc ng dng ring bit.
DIME-II System Clocks
Module BenADDA DIME-II c th to ra ba h thng clock cho FPGA, cc
clock c gi l CLKA, CLKB v CLKC. Cc tn hiu clock c to ra trn bo
mch ch DIME-II v c a vo vng module ni t module BenADDA DIME-
II.Cc clock ny c th c iu khin bi ngi dng v c a n cc chn
Global Clock cung cp mt cch linh hot nht cho FPGA. Tuy nhin cn ch rng
chc nng ca cc DIME-II clock ny c xc nh bi bo mch ch. Khi module
BenADDA DIME-II c t vo bo mch ch BenONE-Kit, khi trong cu hnh
KIT XtremeDSP Development Kit, cc clock ca DIME-II l :
- CLKA: clock do b to dao ng c th lp trnh trn bo mch ch BenONE-
Kit
- CLKB: clock do b to dao ng c th lp trnh trn bo mch ch BenONE-
Kit
- CLKC: kt ni ti mt socket h tr b to dao ng tinh th.
Hnh 20: S h thng clock.
26
LED hin th
XtremeDSP Development Kit c mt s user-definable v cc LED hin th cho
php ngi dng kim tra trng thi hot ng ca b KIT. C cc LED kim tra cu
hnh ngi dng v cc LED hin th trng thi h thng, cu hnh cc giao din v
ngun (Interface LEDs). Cc LED s dng b KIT c ba mu. Mi LED hin th tng
cng ba mu khc nhau: , Xanh v Vng/Dacam. Vi s tr gip ca cc LED hin
th ny ngi thit k c th kim tra mt cch trc quan phn ng ca phn cng i
vi cc yu cu thit k. Tuy ch l mt ng dng nh nhng i khi n c ngha rt
quan trng c bit cho nhng ngi bt u tip cn vi FPGA hay lm chc nng
bo hiu k c trong cc project ln.
Hnh 21: S cc LED trng thi nhn t ngoi.
Hnh 22: Cc LED bn trong Kit Virtex 4.
Trn y ch l nhng nt gii thiu rt s lc v mt s c tnh ca Kit Virtex
4. c th s dng Virtex 4 nh mt cng c h tr c lc cho vic nghin cu, xy
dng cc m hnh th nghim th cn cn phi i su vo tm hiu, nghin cu tng
c tnh nh nh s chn giao tip vi cc tn hiu bn ngoi v cc chn tn hiu
27
giao tip gia cc modul trong Kit... Ngoi ra vic s dng clock trong Virtex-IV cng
rt phc tp i hi ngi nghin cu phi c mt thi gian tm hiu v lm thc tp.
3.2. Cc phn mm chuyn dng h tr kit Virtex 4
3.2.1. FUSE
Phn mm FUSE ca hng Nallatech cho php ngi dng c th cu hnh, iu
khin v thc hin giao tip gia h thng ch v cc phn cng my tnh FPGA ca
Nallatech. Phn mm ny c pht trin c th thit k cc h thng x l phc
tp nh 1 khi thng nht gia phn mm, phn cng v cc ng dng FPGA.
FUSE cung cp mt s giao din, bao gm ngn ng lp trnh DIMEscrip. FUSE
Probe Tool; FUSE cn c pht trin cho cc ngn ng bc cao nh C/C++, Java
hoc Matlab. FUSE c th ci t c trong cc h iu hnh Windows hoc Linux.
Cc c im c bn nht ca FUSE c th k ra nh sau:
* Cu hnh thit b nhanh chng v n gin.
* H tr nhiu Card.
* H tr nhiu giao din.
* H tr cc giao din v iu khin cho cc thit b phn cng ca
Nallatech.
Hnh 23: M t giao tip gia FUSE vi Computer v FPGA.
3.2.2. Matlab v cc gi cng c Xilinx h tr cho Matlab
System Generator
System generator l mt cng c thit k h thng gip cho vic thit k cc ng
dng phn cng trong FPGA v m phng Simulink. l mt mi trng thit k rt
mnh trong vic thit k phn cng. Systerm Generator c kh nng m hnh ha cao
v c th dch cc thit k ca ngi dng sang ngn ng phn cng trong FPGA mt
cch t ng ch vi mt thao tc n gin nh n mt nt. Thm vo System
28
Generator cn cho php xm nhp vo cc ti nguyn trong FPGA mc thp hn,
qua cho php ngi s dng thc hin cc thit k c hiu sut cao.
Vic lp trnh mt b FPGA bng System Generator bao gm cc bc sau: M
phng thit k, to ra mt bn thit k theo ngn ng bc thp c th a cc thit b
phn cng nh FPGA t thit k m phng ny, sau a bn thit k mi to ra ny
vo trong file cu hnh ca FPGA gi l bitsream. Bc cui cng, a thit k phn
cng vo trong bitstream c th thc hin bng cc phn mm khc.
Mt trong nhng mt vt tri ca System Generator so vi cc phn mm khc
l chc nng chy m phng phn cng Co-Simulation, chc nng ny s c ni r
thm trong phn sau.
Cc khi Block Set DSP Xilinx
System Generator xy dng khong hn 90 khi x l tn hiu s (DSP) h
tr ngi dng trong vic m phng cc thit k. Cc khi ny gm cc khi DSP ph
bin nh khi cng, nhn, thanh ghi...Ngoi ra, n cn bao gm cc khi DSP phc
tp hn nh khi sa li tin, FFT, cc b lc v b nh. Cc khi ny lm cho vic
thit k m phng tr nn n gin v thun tin hn nhiu.
Hnh 24: Mt s khi c bn h tr Matlab cung cp bi Xilinx.
Cc thut ton trong Matlab c th kt hp cht ch vo trong System Generator
thng qua AccelDSP. AccelDSP bao gm cc thut ton mnh c th chuyn cc thit
k dng du chm ng (floating-point) trong Matlab sang dng du chm c nh
(fix-point) l loi hay c dng trong System Generator. Ngoi ra System generator
cn bao gm khi Mcode cho php ngi dng s dng cc thut ton khng c trong
Matlab thit k v thc hin cc hot ng iu khin n gin.
nh gi, c lng ti nguyn h thng
System Generator cung cp khi c lng ti nguyn cho php nh gi mt
cch nhanh chng cc ti nguyn dng cho thit k trc khi thc hin n trong thc
t. iu ny c li ch rt ln i vi c vic thit k phn mm ln phn cng gip
29
cho cc nh thit k c th tn dng ti a cc ti nguyn trong FPGA (ln n 550 b
nhn trong thit b Virtex 5).
Hnh 25: Ca s c lng ti nguyn.
M phng phn cng Co-Simulation
Cc khi blocksets c h tr trong System Generator cho php ngi dng xy
dng cc thit k m phng vi chnh xc cao. Tuy nhin cc k s thit k vn
mun xem xt mt cch chi tit vic thit k ca mnh chy trong phn cng nh th
no. System Generator cung cp giao din m phng Cosimulation gip kt hp cht
ch v trc tip vic chy thc t trn FPGA vo m phng simulink. thc hin m
phng Cosimulation, trc ht ta a thit k vo bitstream, sau System Generator
t ng hp nht cu hnh phn cng FPGA vi bitstream tr li thit k m phng
gi l khi run-time. Khi thit k c m phng trong mi trng Simulink, kt qu
ca thit k cng c tnh ton trong phn cng. iu ny cho php chy th cc
thit k trong phn cng tht s v lm tng tnh thc t cho cc m phng.
Kh nng kt hp cc mi trng thit k
System Generator cung cp 1 mi trng thng nht cho cc thit k DSP
FPGAs, cho php cc thnh phn nh c vit bi cc ngn ng khc nhau nh RTL,
Simulink, Matlab v C/C++ c th lm vic cng nhau trong cng mt thit k.
System Generator h tr khi black box cho php a RTL vo thc hin m phng
phn mm v phn cng bng c ModelSim hoc Xilinx ISE Simulator.
Nh vy, vi cng c l Kit Virtex 4 ta khng ch c mt phn cng hin i,
chuyn dng vi lng ti nguyn FPGA ln m cn km theo l nhiu cng c h
tr rt mnh nh System Generator, Co-Simulation cho php ta d dng trin khai
cc nghin cu, thit k.
30
Hnh 26: S m t kh nng kt hp gia cc mi trng thit k.
31
CHNG 4: THC HIN M HNH THIT K VI KIT VIRTEX-4
(Thit k b pht m Walsh cho h o knh MIMO)
4.1. Gii thiu
Vic thit k FPGA thc hin cc chc nng theo mt yu cu no bng
ngn ng VHDL tit kim ti nguyn FPGA tr ln rt ph bin v mang li
nhng li ch r rt. Tuy nhin trong thc t c nhng m hnh ln nh trong cc m
hnh thu pht tn hiu MIMO (Multiple Input, Multiple Output) i hi ngi thc
hin phi thc hin mt khi lng cng vic rt ln vi vic vit cu lnh VHDL m
i khi mc ch ch l kim tra tnh kh thi ca m hnh nu ra. Hn na, vi cng
ngh FPGA pht trin nh ngy nay th ti nguyn trong chip FPGA i vi cc m
hnh nh th khng cn l vn qu quan trng. Xilinx l hng i tin phong trong
lnh vc pht trin cc cng c b tr cho cc kit chuyn dng vi cng c System
Generator nh gii thiu chng 3 nhm gim nh cng vic cho ngi thit k
h thng, ng thi gip ngi thit k bin nhng m hnh m phng tr thnh m
ngun c th nhng trc tip vo trong phn cng (FPGA) Tt nhin iu ny c th
khin m ngun ca thit k di hn v tn ti nguyn phn cng hn nhng n li
mang li gi tr rt ln l rt ngn thi gian trong qui trnh thit k. Chng ny s gii
thiu v cch s dng cng c h tr system generator thc hin mt m hnh thit
k thng qua vic thc hin mt m hnh pht tn hiu qua m ha Walsh.
4.2. Hai khi chc nng chnh trong s
4.2.1. Khi to m Walsh
Hnh 27: Khi to d liu Walsh.
4.2.1.1. L thuyt v m Walsh
M Walsh c chiu di n =2
k
l mt tp cc t m trc giao hon ton c th
c nh ngha bi ma trn hng 2
k
x 2
k
. Vi ma trn ban u 1 x 1 l H
1
= [0],
cc ma trn Hadamard th t cao hn c th ly t ma trn trc n theo cng thc
tng qut sau:
H k
2
=
1
]
1

1 1
1 1
2 2
2 2
k k
k k
H H
H H
V d:
32
H
1
=[0]
H
2
=
1
]
1
1 0
0 0

H
4
=
1
1
1
1
]
1
0 1 1 0
1 1 0 0
1 0 1 0
0 0 0 0

Do vy cc t m Walsh biu din m lng cc ( 1 t ) l
[ ]
1
2
4
1
1 1
1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
H
H
H
+
+ +
1
1
+
]
+ + + +
1
1
+ +
1
1 + +
1
+ +
]
* c im
+ u im
Tt c cc t m u trc giao ln nhau hay cc cp t m bt k u bng 0.
+ Nhc im
- Cc m khng n, nh t tng quan hp.
- Tri khng bao trm ht di thng tuy nhin bao trm ht thnh phn tn s
ri rc.
- Tng quan cho khng lun lun bng 0 cho cc ng dng khng ng b.
- V cu trc c bit c sn trong m Walsh n c bit nh tng quan ca
tp hp vi 2
k
t m Walsh tnh ton kt qu vi phc tp O(n.logn) s dng
bin i Hadamard nhanh (FHT). FHT c cu trc cnh bm (butterfly) tng
t bin i Fourier nhanh (FFT). Nhng FHTc cc h s l 1 t tt hn hm lu
tha phc.
Gii m (m ph c bn gii m Walsh)
M Walsh c gii m tt nht bng b gii m Walsh vi vic tnh ton c
nh, phc tp. Trong phn ny em xin gii thiu phng php hiu qu tng ng
tnh ton phc v BER da trn cu trc ton hc ca m Walsh.
33
Mt ma trn tng qut cho m nh phn tuyn tnh C l ma trn G c cc hng
l c s ca C. Do vy cc t m trong cu trc nh phn c th c tnh ton tng
qut nh sau:
C = xG vi mi ma trn hng nh phn x c dng 1 x k.
Ma tn tng qut m Walsh (6,64) c s dng trong IS-95 l 6 x 64, gm
c 6 hng v 64 ct.
G=
1
1
1
1
1
1
1
1
1
]
1
1 1 0 1 0 1 0
1 0 0 1 1 0 0
1 . . . 1 1 0 0 0 0
1 0 0 0 0 0 0
1 0 0 0 0 0 0
1 0 0 0 0 0 0
T ma trn tng qut ny ta c th gii m ho Walsh m khng kim tra ton
b cc t m.
Gii m cc b (Local Decoding)
Cu trc c bit ca m Walsh cho php nh gi 6 bit li vo m ch cn
quan st duy nht hai trong 64 Symbol ca t m Walsh c nhn, thng qua b
x l gi l Local Decoding, tnh ton phc v truyn t m tt.
hiu cng ngh ny ta t nhn Symbol ca cc t m l c= [c
0
, c
1
, c
2
, .,
c
63
]. Cc gi tr l gi tr thp phn ca p ng nh phn vect ct trong ma trn
G. Mc ch chng ta gii m cc v tr 0 ca vect x = [x
0
, x
1
, x
2
, x
3
, x
4
, x
5
] ni
nhn khi khng c nhiu. Ta c th thu c gi tr ca x
0
bng cch cng module
2 vi bt k thnh phn t m c
i
v c
j
m i, j l cc p ng ct trong G khc duy
nht v tr cc bt 0.
( )
5 5 5
0 0 0
i j s si t tj s si sj
s t s
c c x G x G x G G

_ _

, ,

( )
( )
5
0 0 0 0
1
=x
i i s si si
s
G G x G G x

34
4.2.1.2. Thc hin trong thit k
Ma trn Hadamard dng trong s l:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
]
1
0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0
1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B to m Walsh trong s l b to m Walsh (4,16) v (3,16) (y ch l mt
la chn ngu nhin v c th thay i d dng trong thit k) tc l dng hng th 4
v th trong ma trn Hadamard 16. Khi biu din di dng lng cc th ta c:
[-1 1 1 -1 -1 1 1 -1 -1 1 1 -1 -1 1 1 -1]
v [-1 -1 1 1 -1 -1 1 1 -1 -1 1 1-1 -1 1 1]
Cc gi tr c np vo khi ROM th hin mt chui Walsh s l chui lin tip cc
bit 0 v 1. Vi yu cu thit k cho knh MIMO vi hai ng tn hiu qua b m
Walsh th ta chn hai chui Walsh (4,16) v (3,16) nh sau:
H(4,16): [0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0]
H(3,16): [0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1]
4.2.1.3. S v kt qu m phng b to 2 dy Walsh (4,16) v (3,16)
35
Hnh 28: S m phng b to Walsh.
Kt qu m phng:
Hnh 29: Kt qu m phng b to Walsh (4,16) v (3,16).
4.2.2. Khi m ha cosin tng (Raised-Cosine)
4.2.2.1. L thuyt
Trong cc h thng truyn dn, tn hiu di nn c bn (baseband) c iu ch
ln sng mang truyn i. Vic lc tn hiu xy ra mt s giai on trong qu trnh
truyn dn. Bn thn tn hiu baseband b hn ch bng thng bi vic lc ngn
vic to ra cc tn hiu di bn (sideband) vt qu trong qu trnh iu ch. Tn hiu
iu ch c lc bng thng tip theo trong qu trnh khuch i ca my pht.
ni m cc tuyn truyn (hu tuyn, v tuyn) to thnh knh truyn th p tuyn tn
s ca knh truyn cng phi c tnh ti. pha thu, vic lc bng thng tn hiu ti
l cn thit loi b nhiu (noise) c a vo giai on ny. Nh vy tn hiu i
qua mt s giai on lc v nh hng ca chng ti dng sng s phi c tnh ti.
36
Trn ton b tuyn truyn dn t my pht ti my thu ph ca xung u ra my thu
V(f) c xc nh bi ph ca xung u vo Vi(f), p tuyn b lc ca my pht
H
T
(f), p tuyn tn s ca knh H
CH
(f), v p tuyn b lc my thu H
R
(f). Hnh 30
minh ha iu ny, v ta c phng trnh:
V(f) = Vi(f) H
T
(f) H
CH
(f) H
R
(f) (4.1)
Hnh 30: Cc thnh phn ph tn s ca phng trnh 8.
Cc thnh phn in cm v in dung l cc thnh phn vn c ca qu trnh
lc. Chng khng tiu hao nng lng tn hiu, nhng nng lng c tun hon
theo chu k gia in trng, t trng v tn hiu. Thi gian cn thit cho qu trnh
trao i nng lng ny lm cho mt phn ca tn hiu b tr, do vy cc xung hnh
vung i vo pha my pht c th c dng "hnh chung" v dao ng khi n i ra
pha my thu. Hnh 31a minh ha iu nu. V thng tin c m ha s di dng
sng nn mo xut hin trong dng xung l khng quan trng cho ti khi my thu cn
phn bit c cc xung nh phn 1 vi cc xung nh phn 0. Vic ny i hi dng
sng phi c ly mu cc khong cch ng xc nh ng cc tnh ca n.
Vi dng sng lin tc, cc ui to thnh t hnh chung t tt c cc xung trc
c th kt hp can nhiu vi xung ring cn ly mu. Hin tng gi l can
nhiu gia cc symbol (Intersymbol Interference ISI) v n c th gy li trong xc
nh cc tnh ca tn hiu. Khng th loi b cc hnh chung nhng c th to dng
cc xung sao cho vic ly mu xung cho xy ra khi cc ui cc im ct cho
bng khng nh minh ha hnh 31b. cng l ni dung ca cc nh lut Nyquist
v loi b nh hng ca can nhiu gia cc symbol. Trong thc t khng th to dng
xung hon thin, do vy s c ISI, nhng n c th c gim n mc nh c th b
qua.
Vic to dng xung c thc hin bng cch kim sot ph ca xung thu c qua
iu chnh cc thnh phn c lin quan nh trnh by trong cng thc (4.1). Mt m
hnh l thuyt ca ph thch ng vi vic l p tuyn (hoc b lc) cosin tng:
B lc cosin tng l mt b lc in t c th, thng c s dng to dng xung
trong iu ch s do kh nng ti thiu ha ISI ca n. Tn ca b lc bt ngun t
mt thc t l phn khc khng ca ph tn s trong dng n gin nht ca n (=1)
l hm cosin, tng ln pha trn ca trc ngang f.
37
H
T
(f)
H
CH
(f) H
R
(f)
1/2T
A
A
f
f
(a
(b
Hnh 31: a, Dng hnh chung ca xung
b, Ly mu trnh ISI
M t ton hc:
B lc cosin tng l mt thc hin ca b lc Nyquist thng thp, c tnh cht i
xng theo trc ng. Ph ca n biu hin i xng l xung quanh gi tr (1/2T), vi T
l chu k symbol ca h thng thng tin. Trong min tn s b lc c m t bi
cng thc (4.2), l hm hnh chung (hnh 32). N c c trng bi hai gi tr: h s
roll-off , v chu k lp ca symbol T (T=1/Rs vi Rs l tn s symbol).
Hnh 32: p tuyn bin (tn s) ca b lc cosin tng vi cc h s roll-off khc
nhau
38
=0
=0.35
=0.25
=1
H(f)
1/T
f
t
t

1 0
2
1
2
1
,
_ _ _ , 0
)
2
1
( c o s 1
2
1
2
1
, 0 . 1
) (

<
'
1
]
1
,
_
T
f
T
l a i c o n h o p t r u o n g
T
f
T
T
f
f H
(4.2)
p ng xung (p tuyn thi gian) ca b lc c cho bi cng thc (4.3), l
hm sin chun ha (hnh 33).
2
2 2
4
1
cos(
) ( sin ) (
T
t
T
t
T
t
c t h
(4.3)
A
f
Hnh 33: p tuyn xung ca b lc cosin tng vi cc h s roll-off khc nhau.
H s roll-off
H s roll-off, , l php o bng thng vt qu ca b lc, c ngha l bng
thng b chim ngoi bng thng Nyquist (1/2T).
Nu k hiu bng thng Nyquist l f th:
f T
R
f
T
f
s

2
2 2
1
(4.4)
vi Rs = 1/T l tn s symbol.
39
t
h(t)
Cc th ch ra s thay i ca p tuyn bin khi thay i gia 0 v 1, v
s thay i tng ng vi p tuyn xung. Ta thy mc gn sng min thi gian tng
khi gim. T cc th ta cng thy c th gim bng thng vt qu ca b lc khi
gim (hnh 32) nhng gi t ca vic ko di p tuyn xung, c ngha l ko di
khong thi gian gy can nhiu gia cc symbol k nhau (hnh 33).
= 0
Khi tin ti khng min roll-off tr nn v cng hp, v vy khi 0 lim H(f)
= rect (fT), vi rect(.) l hm ch nht, p ng xung c dng sinc(t/T). iu ny c
ngha l n hi t ti b lc l tng c cc vch dng ng.
= 1
Khi =1 phn khc khng ca ph l cosin tng thun ty, dn n cng thc
n gin (4.5).

[ ]
'
l a i c o n h o p t r u o n g
T
f f T
f H
_ _ _ , 0
1
, ) c o s ( 1
2
1
| ) (
1

(4.5)
Bng thng
Bng thng ca b lc cosin tng c nh ngha nh phn khc khng ca ph
ca n, c ngha l:
BW = (1/2) Rs (1 + ) (4.6)
ng dng
Hnh 34 biu din dy cc xung cosin tng lin tip vi ISI = 0. Khi c s
dng lc symbol stream, b lc Nyquist c tnh cht loi b ISI v p tuyn xung
ca n bng khng tt c cc gi tr nT (vi n l s nguyn), tr gi tr n=0. Do vy
nu dng sng pht c ly mu chnh xc my thu th cc gi tr symbol gc c
khi phc hon ton. Tuy nhin hu ht cc h thng thng tin thc t phi s dng b
lc phi hp loi b nh hng ca nhiu trng. C ngha l phi tun theo iu
kin:
) ( ) ( ) ( ), ( ) (
*
f H f H f H hay f H f H
T R
T
R

(4.7)
tha mn iu kin (4.7) trong khi vn m bo ISI bng khng, b lc cn
bc hai cosin tng thng c s dng hai pha pht v thu ca h thng thng tin.
Khi p tuyn ton b ca h thng s l cosin tng.
40
t
T 2T 3T -T -2T -3T
h(t)
Hnh 34: Cc xung cosin tng lin tip biu th ISI bng 0.
Tm li, b lc cosin tng l mt dng b lc in t c th, c thit k
khc phc can nhiu gia cc symbol (ISI), gip cho h thng s trnh nhm ln khi
xc nh symbol. Thng s quan trng nht ca b lc l h s roll-off , , v chu k
symbol, T. Khi thay i th bng thng vt qu ca b lc cng thay i V
ngha vt l c th hiu nh sau: khi min rol-off cng hp ( 0) th bng thng
vt qu gim, bng thng thc t ca ton tuyn truyn gim, nhiu thnh phn ph
ca xung vung i qua tuyn s b ct dn n dng xung b mo tng ng vi dao
ng nhiu chu k trong p tuyn xung, d gy can nhiu gia cc xung lin k. Khi
min roll-off tng th qu trnh xy ra ngc li, p tuyn xung gn hn, kh nng ISI
t hn nhng bng thng b chim l ln hn, hiu sut s dng bng thng v mt
tng th s km hn. Ty theo phng thc truyn dn (v tinh, cp, mt t) cng
nh s trng thnh ca cng ngh m s c cc gi tr khc nhau, khi hiu sut
s dng bng thng cng khc nhau.
4.2.2.2. Thc hin trong thit k
Trong thit k b lc Raised Cosine c to nn bi khi FIR Compiler
v1_0. Khi ny c chc nng cu trc mt b lc FIR trong FPGA hoc c th cu
trc mt b lc FIR t cc slices c vng ti nguyn DSP l cc khi DSP48. c
th thit k c mt b lc theo mun ta phi cn thm khi FDATool trong
blockset ca Xilinx (khng phi khi FDATool trong blockset ca Simulink).
Hnh 35: Hai khi FIR Compiler v1_0 v FDATool ca Xilinx.
cu hnh cho b lc ta nhy p vo khi FDATool v la chn cc tham
s: B lc Raised-Cosine, tn s F
s
, tn s ct F
c
, v h s Roll-off trn ca s giao
din ca FDATool nh hnh 36:
41
Hnh 36: Ca s giao din FDATool.
Sau chn Design Filter c c cc h s ca b lc. cc h s ny
c y vo cu hnh trong khi FIR Compiler v1_0 c hai cch
Cch th nht: Xut cc h s ny ra Workspace vi cc h s l mt bin
mng vi mt tn no (VD l Num nh hnh 37).
Hnh 37: a h s b lc FIR t FDATool.
ng ca s FDATool li.
Tip , FIR Compiler v1_0 nhn c cc h s ny ta nhy p vo b lc FIR
Compiler v1_0 s xut hp thoi sau:
42
Hnh 38: Cc la chn trong properties ca FIR Compiler c c h s t
Workspace.
Ta la chn cc tham s ph hp nh c khoanh trn hnh ri ng ca s ny
li.
Nh vy ta c c mt b lc Cosin tng vi cc h s c thit k t
cng c FDATool.
Cch th 2: Vi cch ny ta cng thit k b lc t FDATool nhng khng y cc h
s ra Workspace m t lnh xlfda_numerator(Ten_cua_khoi_FDATool) trong
properties ca khi FIR Compiler v1_0 sau la chn Filter type l interpolation nh
hnh 39 di y:
Hnh 39: Cc la chn trong properties ca FIR Compiler c c h s trc tip
t FDATool.
Sau ng ca s ny li v mt b lc Cosin tng c cu hnh t cc h
s c thit k t FDATool. Ngoi ra, ta cng c th cu hnh b lc bng ngun ti
nguyn DSP48 c sn trong Kit dng cho cc ng dng DSP vi nhiu li ch. Tuy
nhin trong bi kha lun ny s khng cp n phng php ny.
4.2.3. Khi to d liu
43
Trong thc t d liu ny phi c a t ngoi vo thng qua b ADC ca
Kit Virtex 4. Tuy nhin do y cha phi l mt thit k vi mt mc ch thc hin
trong mt ng dng c th nn d liu s c to ty bn trong Kit Virtex 4. D
liu ny l d liu s c chn ty c xy dng t cc khi Counter, ROM, v
cc b Time Division. Trong , d liu ty c np vo ROM, khi Counter dng
cp xung nhp cho ROM y d liu ra, cc b Time Division h tn s ca d
liu phi hp vi chui Walsh pht ra t b to Walsh. Trong thit k ny dng Walsh
16 nn tc d liu s chm hn tc Walsh 16 ln. Mi b Time Division s chia
i tn s ca d liu nn trong thit k ny cn dng 4 b Time Division (B to d
liu ny cng c th c to bng nhiu cch khc nhau).
Hnh 40: S khi b to d liu.
4.2.4. Cc khi khc
Trong s cn dng mt s khi khc nh b DAC, XOR. Ngoi ra quan trng
nht l khi System Generator dng qun l cp tn hiu cho ton b cc khi trong
s .
Hnh 41: Khi XOR v System Generator.
Cch cu hnh cho khi System Generator s c ni chi tit hn phn thc
hin m hnh thit k s cp di y.
4.3. M hnh thit k v kt qu thu c
44
4.3.1. M hnh m phng vi cc khi trong gi cung cp bi Xilinx v trong
System Generator
Hnh 42: M hnh thit k b to ra 2 dy tn hiu.
Cu hnh trong System Generator c ch ra nh hnh 37 di y:
Hnh 43: Cc tham s cu hnh trong System Generator.
4.3.2. Kt qu m phng
45
Dng xut ra (HDL Netlist, Bitfile)
Tn Kit
ng dn lu cc file s xut ra
Ngn ng m t phn cng s xut ra
Chu k m phng.
Chn Clock dng trong thit k
Hnh 44: Kt qu m phng 1 chui tn hiu c m ha vi 2 dy Walsh khc nhau.
Tn hiu pha trn l chui tn hiu 0101 c m ha vi dy Walsh (4,16)
v c lc qua b lc Cosin tng.
Tn hiu pha bn di l chui tn hiu 0101 c m ha vi dy Walsh
(3,16) v c a qua b lc Cosin tng.
4.3.3. Thc hin chng trnh trn Kit Virtex 4 v kt qu thu c
4.3.3.1. Thc hin trn Kit Virtex 4
thc hin c trn Kit Virtex 4 t s m phng c xy dng ta
cn lm cc bc sau:
- Cu hnh cho System Generator nh ch ra phn 4.3.1.
- To ra m ngun t s m phng.
- Dng phn mm ISE ca Xilinx bin dch chng trnh v gn chn cho cc tn
hiu vo ra.
- To ra bitfile t ISE (file ny s c np vo FPGA).
- Dng phn mm h tr FUSE m card (m giao tip gia my tnh v FPGA).
- Cu hnh clock cho Kit thng qua thao tc np file nh ngha clock FPGA s thc
hin trong thit k.
- Np thit k vo trong FPGA.
4.3.3.2. Kt qu thu c
46
Hnh 45: Quan st tn hiu m ha Walsh pht ra t Kit Virtex 4.
nh gi kt qu
Kt qu m phng v kt qu quan st c khi thc thc hin trn Kit thc
ph hp vi kt qu tnh ton l thuyt.
Vic thit k v thc hin thnh cng b pht ra hai dng m Walsh cho knh
MIMO dng cng ngh FPGA hon ton c th p dng trong nhng m hnh khc.
S dng Kit Virtex 4 cng vi cc cng c h tr i km thit k FPGA l
mt phng php thit k n gin, linh hot v hiu qu.
KT LUN
47
K thut MIMO vi nhng u im ca n ang ngy cng c ng dng
rng ri cng vi cc nhc im ca k thut ny cng dn dn c khc phc
trong qu trnh nghin cu v thc hin. Vi vic s dng FPGA xy dng mt h
Testbed lm gim ng k cho qu trnh thc hin mch in t ng thi tnh kh
thi cng tng ln rt nhiu. Vi kh nng ti lp trnh ca FPGA ta c th d dng thay
i v trin khai cc thut ton x l m khng cn ngh n vic thay i phn cng.
ti kha lun ny tuy mi ch thc hin c mt phn nh trong m hnh
xy dng mt h Testbed MIMO nhng n s l tin cho vic nghin cu v hon
thnh tip nhng chc nng cn li trong h.
Vi vic thc hin thit k thnh cng b m ha Walsh trong knh truyn
MIMO vi hai ng tn hiu ta c th hon ton p dng c vi cc h MIMO c
s lng knh truyn ln hn. Vi thnh cng ny th nhim v xy dng hon thin
mt b Testbed MIMO hon chnh s sm thc hin c.
c bit qua qu trnh tm hiu v lm thc nghim em thu c nhiu kin
thc v cng ngh FPGA, cch s dng Kit chuyn dng Virtex 4 l nhng kin thc
m khng phi bt k sinh vin no trong trng cng c tip cn.
Mt ln na em xin c cm n TS Trnh Anh V v anh CN.V Xun Thng
tn tnh ch bo em v kin thc cng nh to mi iu kin thun li em hon
thnh ti kha lun ny.
TI LIU THAM KHO
48
[1] Mani B. Srivastava. VHDL tutorial. UCLA EE.
[2] System Generator for DSP (Getting started Guide, Reference Guide, User Guide).
Xilinx.
[3] Nguyn Trng Hi. Bi ging Verilog. H K thut cng ngh TPHCM.
[4] Nguyn Vit Knh, Trnh Anh V. Thng tin s. NXBGD.
[5] V Xun Thng Knh truyn MIMO v b thu pht cho h o th knh. Kha lun
tt nghip, trng H Cng ngh - HQGHN.
[6] Website:
www.xilinx.com
www.VNeEpress.com
www.wikipedia.org
MC LC
49
Khi logic .............................................................................................................. 6
Hnh 3: Khi logic trong FPGA ............................................................................ 6
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