Simplification of Sequential Circuits

Equivalent State State Reduction Implication Table Minimization Procedure

Simplification of Sequential circuits

Equivalent State :
States S1,S2..Sj are equivalent if and only if for every possible input sequence, the same output will be produced regardless of whether S1,S2..Sj is the initial states

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

Simplification of Sequential circuits

Pair wise Si and Sj are equivalent if and only if for every possible input Ip, 1. Output produced by Si is equal to output produced by Sj 2. Next state Sk and Sl are equivalent

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

Simplification of Sequential circuits

A Equivalent Relation on S is - Symmetric Si R Sj => Sj R Sj - Reflexive Si R Si for all i - Transitive Si R Sj and Sj R Sk => Si and Sk

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

State Reduction:

To determine equivalent states: 1. Inspection 2. Partitioning 3. Implication Table

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

State Reduction: Inspection: Trivial Partitioning:

Pk = (S1S3)(S2S4)(S5), S1 and S3 are k-equivalent.

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

State Reduction:
Partition P1 a. Two or more status in the same block iff their output is identical for each input. 0 A B C P1 = (ABC)(DE) D E
EE270 Simplification of Sequential Circuits Dr. Tri Caohuu 2006 Andy Davis

1 B/0 E/0 E/0 B/1 A/1

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C/1 C/1 B/1 D/0 E/0

Lecture 03

State Reduction:
b. Place 2 or more states in the same block iff for each input value their next states all lie in a single block of Pk-1

P2 = (A)(BC)(DE) x=0 (ABC) x=1 (ABC)

(ABC) (ABC) (DE)

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

State reduction:
c. When Pk+1 = Pk partition. P3 = (A)(BC)(D)(E) stop Pk = equivalent

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

Implication Table
Consider the following example of a state table.

PS
A B C D E F G
EE270 Simplification of Sequential Circuits

NS 0 A D F D B G A 1 B C E F G C F 0 0 0 0 0 0 0 0

Z 1 0 1 0 0 0 1 0
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Dr. Tri Caohuu 2006 Andy Davis

Implication Table
B C D E F G
BF AF BE BF AB BG DG AF EF AB FG DF EF BF EG BD FG

AD

A
EE270 Simplification of Sequential Circuits

F
Lecture 03 11

is caused by conflict in output

Dr. Tri Caohuu 2006 Andy Davis

Implication Table
B C D E F G
BF AF BE BF AB BG DG AF EF AB FG DF EF BF EG BD FG

AD

A
EE270 Simplification of Sequential Circuits

F
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Dr. Tri Caohuu 2006 Andy Davis

Implication Table
B C D E F G
BF AF BE BF AB BG DG AF EF AB FG DF EF BF EG BD FG

AD

A
EE270 Simplification of Sequential Circuits

F
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Dr. Tri Caohuu 2006 Andy Davis

Implication Table

A G ( AGD ) D G
S m = {( ADG )(BF )(C )(E )}
EE270 Simplification of Sequential Circuits Dr. Tri Caohuu 2006 Andy Davis Lecture 03 14

A D

B F } (BF )

State Reduction of Incompletely Specified Circuit

Definition State Si and Sj are compatible iff:

Outputs produced by Si and Sj are the same for each possible input Ip. The next state of Si and Sj must e compatible for each possible input Ip.

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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State Reduction of Incompletely Specified Circuit

Definition:
A maximal compatible is a compatible class that will not remain a compatible class if any state not in the class is added. Compatible class Set of compatible states

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Example
State Table
x A B C D E F G H 0 A/B/G/C/1 A/1 D/G/H/1 C/1 A/E/0 C/C/A/G/D/Dr. Tri Caohuu 2006 Andy Davis Lecture 03 17

EE270 Simplification of Sequential Circuits

Implication Table
B C D E F G H
EE270 Simplification of Sequential Circuits

AC

BG AE AC BC AC AD AC CG AG AD AB AC BD AG DG AE EG GH DE CG CE AC

CD AC CG CH CD

AD AC AG CG AH CD DG AG DH AD DG

CD

G
Lecture 03 18

Dr. Tri Caohuu 2006 Andy Davis

Compatibility Classes
G F E E D C C B A A A (GH) (GH)(FG) (EG)(EH)(GH)(FG) (FG)(EGH) (DG)(FG)(EGH) (CG)(CF)(CE)(CD)(DG)(FG)(EGH) (CEG)(CDG)(CFG)(EGH) (BC)(BG)(CEG)(CDG)(CFG)(EGH) (AE)(AG)(AH)(BC)(BG)(CEG)(CDG)(CFG)(EGH) (AEG)(AGH)(AEH)(BCG)(CEG)(CDG)(CFG)(EGH) (AEGH)(BCG)(CDG)(CEG)(CFG)
Dr. Tri Caohuu 2006 Andy Davis Lecture 03 19

EE270 Simplification of Sequential Circuits

Incompatibility Classes
G F E D D C B B B A A (FH) (FH)(EF) (FH)(EF)(DH)(DF)(DE) (FH)(DH)(DEF) (CH)(FH)(DH)(DEF) (BH)(BF)(BE)(BD)(CH)(FH)(DH)(DEF) (BH)(BDEF)(CH)(FH)(DH) (BDEF)(CH)(BDFH) (AB)(AC)(AD)(AF)(BDEF)(CH)(BDFH) (ABDF)(AC)(BDEF)(CH)(BDFH)

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Merger Diagram for the maximal compatibles

B A C

D H

E G F

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Minimization Conditions
1. 2. 3.

Completeness (coverage) Consistency (closure) Minimality (smallest number of compatibility classes)

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Minimization Procedure
The upper bound U on the number of states in the minimal circuit is:
U = minimum {NSMC, NSOC} NSMC: number of sets of maximal compatibles NSOC: number of states in the original circuit

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Minimization Procedure
The lower bound L on the number of states in the minimal circuit is:
L = maximum {NSMC1, NSMC2, , NSMCi, } NSMCi: number o states in the ith group of the set of maximal incompatibles of the original circuit

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Example
CLOSURE TABLE
X 0 (AEGH) AGH (BCG) BG (CDG) CG (CFG) DG (CEG) AG 1 CDG AEG CEG AEG CEG A B C D E

REDUCED STATE TABLE

X 0 A/1 B/B,C,D,E/1 A/1 C/1 C/1 A/0 D/0 D/0 A/0

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Example
NSMC = 5; NSOC = 8 U = minimum {5, 8} = 5 L = maximum {4, 4, 4, 2, 2} = 4 4K 5

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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Optimal State Assignment

Introduction Guidelines Example

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Introductions
1.
1.

There are differences in hardware cost associating with different state assignments Total number of possible assignments for N
s

N sa =

2 Nff ! ( 2 Nff N s )!

Nff : # of flip/flops Ns : # of states 3. Many state assignment yield the same result. Nua: number of unique assignments

N ua =

( 2 Nff 1)! ( 2 Nff N s )!Nff !

Dr. Tri Caohuu 2006 Andy Davis Lecture 03 28

EE270 Simplification of Sequential Circuits

Minimum Cost
Minimum gates and input counts Minimum cost circuit Reduced dependency

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

29

State Assignment Rules

R1: State that have same next state for a given input should be given logically adjacent assignments R2: States that are the next state of a single present state, under logically adjacent inputs should be given logically adjacent assignments R3:Two or more present state that produce the same output, for a given input combination should be made adjacent R4: Start with the most transferred to state at 00000 on the K-map. Assign adjacent state according to R1, R2,R3.
EE270 Simplification of Sequential Circuits Dr. Tri Caohuu 2006 Andy Davis Lecture 03 30

Example
Given the state table, Consider all unique assignments Find the optimal assignment Verify using T f/fs
A1 A B C D 00 01 11 10 A2 00 11 01 10 A3 00 10 01 11
Dr. Tri Caohuu 2006 Andy Davis Lecture 03 31

A B C D

0 C/0 C/0 B/0 A/1

1 D/0 A/0 D/0 B/1

EE270 Simplification of Sequential Circuits

Example- cont.
Assignment 1
T1 = x + y2 T2 = y1 x + y2 x + x y1 y2

Assignment 2

T1 = y2 + y1 x + y1 x T2 = y1 x + y2 x + x y1 y2

Assignment 3

T1 = xy1 + y1 y2 + y1 x + y1 y2 T2 = x + y1 y2 + y1 y2

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

32

Optimal State Assignment

Introduction Guidelines Example

33

Introductions
1.
1.

There are differences in hardware cost associating with different state assignments Total number of possible assignments for N
s

N sa =

2 Nff ! ( 2 Nff N s )!

Nff : # of flip/flops Ns : # of states 3. Many state assignment yield the same result. Nua: number of unique assignments

N ua =

( 2 Nff 1)! ( 2 Nff N s )!Nff !

Dr. Tri Caohuu 2006 Andy Davis Lecture 03 34

EE270 Simplification of Sequential Circuits

Minimum Cost
Minimum gates and input counts Minimum cost circuit Reduced dependency

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

35

State Assignment Rules

R1: State that have same next state for a given input should be given logically adjacent assignments R2: States that are the next state of a single present state, under logically adjacent inputs should be given logically adjacent assignments R3:Two or more present state that produce the same output, for a given input combination should be made adjacent R4: Start with the most transferred to state at 00000 on the K-map. Assign adjacent state according to R1, R2,R3.
EE270 Simplification of Sequential Circuits Dr. Tri Caohuu 2006 Andy Davis Lecture 03 36

Example
Given the state table, Consider all unique assignments Find the optimal assignment Verify using T f/fs
A1 A B C D 00 01 11 10 A2 00 11 01 10 A3 00 10 01 11
Dr. Tri Caohuu 2006 Andy Davis Lecture 03 37

A B C D

0 C/0 C/0 B/0 A/1

1 D/0 A/0 D/0 B/1

EE270 Simplification of Sequential Circuits

Example- cont.
Assignment 1
T1 = x + y2 T2 = y1 x + y2 x + x y1 y2

Assignment 2

T1 = y2 + y1 x + y1 x T2 = y1 x + y2 x + x y1 y2

Assignment 3

T1 = xy1 + y1 y2 + y1 x + y1 y2 T2 = x + y1 y2 + y1 y2

EE270 Simplification of Sequential Circuits

Dr. Tri Caohuu 2006 Andy Davis

Lecture 03

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