Scribd Logo
Upload

Welcome to Scribd!

  • HowTo Read Simulation Code

    Uploaded by

    Islam Sehsah
    28 views4 pages
    This document provides instructions on how to use force commands in VHDL simulation code to assign values and delays to different signals. It includes examples of force commands for assigning a clock with 100ns period to the clk signal, assigning a value of 1 to the wr signal with 0ns delay, and assigning a value of 0000000 to the addr signal with 100ns delay. The document also describes how to implement these forced signal assignments in the simulator user interface.

    Original Description:

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document provides instructions on how to use force commands in VHDL simulation code to assign values and delays to different signals. It includes examples of force commands for assigning a clock with 100ns period to the clk signal, assigning a value of 1 to the wr signal with 0ns delay, and assigning a value of 0000000 to the addr signal with 100ns delay. The document also describes how to implement these forced signal assignments in the simulator user interface.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    28 views4 pages

    HowTo Read Simulation Code

    Uploaded by

    Islam Sehsah
    This document provides instructions on how to use force commands in VHDL simulation code to assign values and delays to different signals. It includes examples of force commands for assigning a clock with 100ns period to the clk signal, assigning a value of 1 to the wr signal with 0ns delay, and assigning a value of 0000000 to the addr signal with 100ns delay. The document also describes how to implement these forced signal assignments in the simulator user interface.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 4

    How To Read Simulation Code Forces

    In

    VHDL
    Practical Exam Guide

    force -freeze sim:/ram_128_8/clk 1 0, 0 {50 ns} -r 100


    force -freeze sim: Force Command ram_128_8 Program Name clk 1 0, 0 {50 ns} -r 100 Assign Clock with 100ns period to Signal clk

    Done By:
    View Signals Click on clk signal Edit Clock Ok

    force -freeze sim:/ram_128_8/wr 1 0


    force -freeze sim: Force Command ram_128_8 Program Name wr 1 0 Assign Value 1 to Signal wr with 0ns Delay

    Done By:
    View Signals Click on wr signal Edit Force Value = 1 , Delay = 0 Ok

    force -freeze sim:/ram_128_8/addr 0000000 100


    force -freeze sim: Force Command ram_128_8 Program Name addr 1 0 Assign Value 0000000 to Signal addr with 100ns Delay

    Done By:
    View Signals Click on addr signal Edit Force Value = 0000000 , Delay = 100 Ok

    force -freeze sim:/rom_128_8/addr 1111101 1400


    force -freeze sim: Force Command rom_128_8 Program Name addr 1111101 1400 Assign Value 1111101 to Signal addr with 1400ns Delay

    Done By:
    View Signals Click on addr signal Edit Force Value = 1111101 , Delay = 1400 Ok

    force -freeze sim:/tlc/start 1 300


    force -freeze sim: Force Command tlc Program Name start 1 300 Assign Value 1 to Signal start with 300ns Delay

    Done By:
    View Signals Click on start signal Edit Force Value = 1 , Delay = 300 Ok

    force -freeze sim:/suez/sensor_b 1 1600


    force -freeze sim: Force Command suez Program Name sensor_b 1 1600 Assign Value 1 to Signal sensor_b with 1600ns Delay

    Done By:
    View Signals Click on sensor_b signal Edit Force Value = 1 , Delay = 1600 Ok

    You might also like