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9300/DM9300 4-Bit Parallel-Access Shift Register: General Description
9300/DM9300 4-Bit Parallel-Access Shift Register: General Description
June 1989
Features
Y Y Y Y Y Y Y
Fully buffered inputs Direct overriding clear Synchronous parallel load Parallel inputs and outputs from each flip-flop Positive edge-triggered clocking J and K inputs to first stage Typical shift frequency 39 MHz
Connection Diagram
Dual-In-Line Package
Order Number 9300DMQB 9300FMQB or DM9300N See NS Package Number J16A N16E or W16A
TL F 6600 1
Function Table
Inputs Clear L H H H H H H Shift Load X L H H H H H Clock X Serial J K X X X H L H L P0 X a X X X X X X X X L L H H Parallel P1 X b X X X X X P2 X c X X X X X P3 X d X X X X X QA L a QA0 QA0 L H QAn QB L b QB0 QA0 QAn QAn QAn Outputs QC L c QC0 QBn QBn QBn QBn QD L d QD0 QCn QCn QCn QBn QD H d QD0 QCn QCn QCn QCn
u
L
u u u u
H e High Level (Steady State) L e Low Level (Steady State) X e Dont Care
TL F 6600
RRD-B30M105 Printed in U S A
Parameter Min 45 2
Commercial Min 4 75 2 08
b0 8
Nom 5
96 30 0 16 30 30 20 30 0 10 125 0 11 15 13 13 13
b 11
16 30
ns ns ns 70 C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V VCC e Max VI e 0 4V VCC e Max (Note 3) VCC e Max (Note 4) Input CP Input PE Input IIL Low Level Input Current Input CP Input PE Input IOS ICC Short Circuit Output Current Supply Current MIL COM MIL COM
b 20 b 18
Min
Typ (Note 2)
Max
b1 5
Units V V
24 04 1 40 80 92
b1 6 b3 2 b3 7 b 80 b 55
V mA
mA
mA
mA mA
86 92
Note 1 RELEASE TIME tRELEASE is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low to high in order for the flip-flop(s) not to respond Note 2 All typicals are at VCC e 5V TA e 25 C Note 3 Not more than one output should be shorted at a time Note 4 With all outputs open SHIFT LOAD grounded and 4 5V applied to J K and data inputs ICC is measured by applying momentary ground then 4 5V to CLEAR and then to CLOCK Note 5 TA e 25 C and VCC e 5V
Switching Characteristics
Symbol Parameter
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Military Commercial RL e 400X CL e 15 pF Min 30 20 24 37 22 26 30 Max MHz ns ns ns Units
Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Output Clock to Output Clear to Output
30
Schematic Diagram
DM9300
4
TL F 6600 2
16-Lead Ceramic Dual-In-Line Package (J) Order Number 9300DMQB NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N) Order Number DM9300N NS Package Number N16E
16-Lead Ceramic Flat Package (W) Order Number 9300FMQB NS Package Number W16A
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