Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-1

LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY

LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron CMOS technology Summary CMOS Analog Circuit Design, 2nd Edition Reference New material

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-2

CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY Isolation of Transistors The use of reverse bias pn junctions to isolate transistors becomes impractical as the transistor sizes decrease.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-3

Use of Shallow Trench Isolation Technology Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the depletion region at the surface.

Substrate Salicide Well Salicide Trench Isolation

Sh all o w

Substrate Salicide Decreased spacing

n+ Shallow Trench Isolation

p+

p+ Shallow Trench Isolation

n n++

n++ nn+ Shallow Trench Isolation Substrate

070330-03

n-well

p-well

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Sh all ow Iso Tre lat nc ion h

Metal

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-4

Comparison of STI and LOCOS What are the differences between a LOCOS and STI technology?

Comments: If the n+ to p+ spacing is large, the Birds beak can be compensated using techniques such as poly buffered LOCOS At some point as the n+ to p+ spacing gets smaller, the restricted birds beak leads to undesirable stress effects in the transistor. An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+ isolation compared to LOCOS. This is a significant advantage for any process where there are implants before STI.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-5

Shallow Trench Isolation (STI) 1.) Cover the wafer with pad oxide and silicon nitride. 2.) First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns. 3.) Grow a thin thermal oxide layer on the trench walls.
Nitride (1) Silicon

(2)

(3)

4.) A CVD dielectric film is used to fill the trench.

(4)

5.) A chemical mechanical polishing (CMP) step is used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer. 6.) Densify the dielectric material at 900C and strip the nitride and pad oxide.

(5)

(6)
060203-01

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-6

Illustration of a Deep Submicron (DSM) CMOS Technology

Metal Layers 0.8m M8 NMOS PMOS M7 Transistor Transistor M6 M5 7m Polycide 0.3m Polycide Sidewall Spacers M4 Salicide Salicide M3 Salicide M2 M1 STI n+ n+ Source/drain extensions Deep p-well

;;

STI

p+ p+ Source/drain STI extensions Deep n-well p-substrate

031211-02

In addition to NMOS and PMOS transistors, the technology provides: 1.) A deep n-well that can be utilized to reduce substrate noise coupling. 2.) A MOS varactor that can serve in VCOs 3.) At least 6 levels of metal that can form many useful structures such as inductors, capacitors, and transmission lines.
CMOS Analog Circuit Design P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-7

Transistors fT as a function of gate-source overdrive, VGS-V T (0.13m):

70 60 50 NMOS Typical, 25C Slow, 70C Typical, 25C PMOS Slow, 70C

fT (GHz)

40 30 20 10 0 0 100 200 300 |VGS-VT| (mV)

400

500
030901-07

The upper frequency limit is probably around 40 GHz for NMOS with an fT in the vicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-8

Resistors 1.) Diffused and/or implanted resistors. 2.) Well resistors. 3.) Polysilicon resistors. 4.) Metal resistors.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-9

Capacitors Polysilicon-polysilicon capacitors:

Metal-metal capacitors:
Protective Insulator Layer Metal Via Capacitor dielectric Capacitor bottom plate Vias connecting bottom plate to lower metal Vias connecting top plate to top metal Capacitor Top Metal Vias connecting bottom plate to lower metal Top Metal Second level from top metal Third level from top metal Fourth level from top metal
060530-01

Intermediate Oxide Layers

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-10

Inductors Top view and cross-section of a planar inductor:

Top Metal W S Next Level Metal Next Level Metal Top Metal

Vias

Oxide Oxide

D Silicon Substrate

N turns D
030828-01

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-11

TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Major Fabrication Steps for a DSM CMOS Process 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift and anti-punch through implants 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide 10.) Higher level metals, tungsten plugs/vias, and oxide 11.) Top level metal, vias and protective oxide

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-12

Starting Material The substrate should be highly doped to act like a good conductor.

Substrate Gate Ox Oxide p+ p pnn n+ Poly Salicide Polycide Metal

060118-02

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-13

Step 1 - n and p wells These are the areas where the transistors will be fabricated - NMOS in the p-well and PMOS in the n-well. Done by implantation followed by a deep diffusion.

n well implant and diffusion p+

p well implant and diffusion n+

n-well

p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

060118-03

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-14

Step 2 Shallow Trench Isolation The shallow trench isolation (STI) electrically isolates one region/transistor from another.

p+ Shallow Trench Isolation n-well Shallow Trench Isolation

n+ Shallow Trench Isolation p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

060118-04

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-15

Step 3 Threshold Shift and Anti-Punch Through Implants The natural thresholds of the NMOS is about 0V and of the PMOS is about 1.2V. An pimplant is used to make the NMOS harder to invert and the PMOS easier resulting in threshold voltages balanced around zero volts. Also an implant can be applied to create a higher-doped region beneath the channels to prevent punch-through from the drain depletion region extending to source depletion region.
n+ anti-punch through implant p threshold implant p+ anti-punch through implant p threshold implant n+ Shallow Trench Isolation n-well Shallow Trench Isolation p-well Substrate Gate Ox Oxide p+ p pnn n+ Poly Salicide Polycide Metal
060118-05

Shallow Trench Isolation

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-16

Step 4 Thin Oxide and Polysilicon Gates A thin oxide is deposited followed by polysilicon. These layers are removed where they are not wanted.

p+ Shallow Trench Isolation n-well Shallow Trench Isolation

n+ Shallow Trench Isolation p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

060118-06

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-17

Step 5 Lightly Doped Drains and Sources A lightly-doped implant is used to create a lightly-doped source and drain next to the channel of the MOSFETs.

Shallow pImplant

Shallow pImplant

Shallow nImplant

Shallow nImplant

p+ Shallow Trench Isolation n-well Shallow Trench Isolation

n+ Shallow Trench Isolation p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

070321-01

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-18

Step 6 Sidewall Spacers A layer of dielectric is deposited on the surface and removed in such a way as to leave sidewall spacers next to the thin-oxide-polysilicon-polycide sandwich. These sidewall spacers will prevent the part of the source and drain next to the channel from becoming heavily doped.

Sidewall Spacers

Sidewall Spacers

p+ Shallow Trench Isolation n-well Shallow Trench Isolation

n+ Shallow Trench Isolation p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

070321-02

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-19

Step 7 Implantation of the Heavily Doped Sources and Drains Note that not only does this step provide the completed sources and drains but allows for ohmic contact into the wells and substrate.

n+ implant n+ Shallow Trench Isolation

p+ implant p+

p+ implant p+ Shallow Trench Isolation

n+ implant n+

n+ implant n+ n+

p+ implant p+ Shallow Trench Isolation

n-well

p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

070321-03

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-20

Step 8 Siliciding (Salicide and Polycide) This step reduces the resistance of the bulk diffusions and polysilicon and forms an ohmic contact with material on which it is deposited. Salicide = Self-aligned silicide

Polycide Salicide Shallow Trench Isolation n-well Salicide n+ p+ p+ p+ Shallow Trench Isolation Salicide n+

Polycide Salicide n+ n+ p+ Shallow Trench Isolation p-well Substrate

Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

070321-04

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-21

Step 9 Intermediate Oxide Layer An oxide layer is used to cover the transistors and to planarize the surface.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-22

Step 10- First-Level Metal Tungsten plugs are built through the lower intermediate oxide layer to provide contact between the devices, wells and substrate to the first-level metal.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-23

Step 11 Second-Level Metal The previous step is repeated for the second-level metal.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-24

Completed Fabrication After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel metal and a protective layer to hermetically seal the circuit from the environment. Note that metal is used for the upper level metal vias. The chip is electrically connected by removing the protective layer over large bonding pads.

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-25

Scanning Electron Microscope of a MOSFET Cross-section

Tungsten Plug TEOS SOG

TEOS/BPSG

Polycide Sidewall Spacer Poly Gate

Fig. 2.8-20

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-26

Scanning Electron Microscope Showing Metal Levels and Interconnect

Metal 3 Aluminum Vias Tungsten Plugs Metal 2

Metal 1

Transistors

Fig.180-11

CMOS Analog Circuit Design

P.E. Allen - 2010

Lecture 030 DSM CMOS Technology (3/24/10)

Page 030-27

SUMMARY DSM technology typically has a minimum channel length between 0.35m and 0.1m DSM technology addresses the problem of excessive depletion region widths in junction isolation techniques by using shallow trench isolation DSM technology may have from 4 to 8 levels of metal Lightly doped drains and sources are a key aspect of DSM technology

CMOS Analog Circuit Design

P.E. Allen - 2010