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  • EECE488 Analog CMOS Integrated Circuit Design Assignment 1 Due: Tuesday February 8, 2011 at 9:30am

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    This document contains instructions for Assignment 1 of the EECE488 Analog CMOS Integrated Circuit Design course due on February 8th, 2011. It includes 3 problems to solve: 1) analyzing the region of operation and output resistance of a 2-transistor circuit, 2) proving a stacked transistor structure can be viewed as a single transistor, and 3) calculating the output resistance of additional circuits. Students are to determine expressions, prove equivalencies, and perform calculations as directed while considering device parameters. Good luck is wished for completing the assignment problems.

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    This document contains instructions for Assignment 1 of the EECE488 Analog CMOS Integrated Circuit Design course due on February 8th, 2011. It includes 3 problems to solve: 1) analyzing the region of operation and output resistance of a 2-transistor circuit, 2) proving a stacked transistor structure can be viewed as a single transistor, and 3) calculating the output resistance of additional circuits. Students are to determine expressions, prove equivalencies, and perform calculations as directed while considering device parameters. Good luck is wished for completing the assignment problems.

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    11 views2 pages

    EECE488 Analog CMOS Integrated Circuit Design Assignment 1 Due: Tuesday February 8, 2011 at 9:30am

    Uploaded by

    konikaka
    This document contains instructions for Assignment 1 of the EECE488 Analog CMOS Integrated Circuit Design course due on February 8th, 2011. It includes 3 problems to solve: 1) analyzing the region of operation and output resistance of a 2-transistor circuit, 2) proving a stacked transistor structure can be viewed as a single transistor, and 3) calculating the output resistance of additional circuits. Students are to determine expressions, prove equivalencies, and perform calculations as directed while considering device parameters. Good luck is wished for completing the assignment problems.

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    Download as PDF, TXT or read online from Scribd
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    EECE488 Analog CMOS Integrated Circuit Design Assignment 1 Due: Tuesday February 8th, 2011 at 9:30am

    1. In the following circuit assume that the bulks of the two NMOS transistors are connected to ground, =0, and 0. a) What is the region of operation of transistor M1? b) Does the region of operation of M1 depend on the relative sizing of the transistors. In other word, does it depend on the values W1, W2, L1, and L2. c) Assume that the Ibias and the transistor sizes are chosen such that the drain voltage of M1 is very close to zero. Find the expression for the output resistance of the circuit seen at the drain of M2 in terms of circuit parameters.

    2. Based on Problem 2.16 of the Razavis book: a) Consider the structure shown in the following figure. Determine ID as a function of VGS and VDS and prove that the structure can be viewed as a single transistor having an aspect ratio W/(2L). Assume = = 0.

    b) Repeat part a for the following structure (assuming both transistors have the same aspect ratio W/L) and show that the structure can be viewed as a single transistor having an aspect ratio of 2W/L.

    3. Calculate the output resistance (VX/IX) of the following circuits. Assume 0 and 0.

    Good luck.

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