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  • 2011 Hw3 Solution

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    This document contains solutions to an ECE152B homework assignment. It discusses circuit timing analysis problems involving calculating slack times, determining minimum clock periods, and designing clock trees to minimize delay from the clock source to flip-flops. The document provides the total delay for a clock tree driving 300 flip-flops with one buffer, as well as an optimized tree with 4 levels of buffers that achieves a delay of 5.1ns.

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    This document contains solutions to an ECE152B homework assignment. It discusses circuit timing analysis problems involving calculating slack times, determining minimum clock periods, and designing clock trees to minimize delay from the clock source to flip-flops. The document provides the total delay for a clock tree driving 300 flip-flops with one buffer, as well as an optimized tree with 4 levels of buffers that achieves a delay of 5.1ns.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    Download as pdf or txt
    41 views3 pages

    2011 Hw3 Solution

    Uploaded by

    praveenkumardr
    This document contains solutions to an ECE152B homework assignment. It discusses circuit timing analysis problems involving calculating slack times, determining minimum clock periods, and designing clock trees to minimize delay from the clock source to flip-flops. The document provides the total delay for a clock tree driving 300 flip-flops with one buffer, as well as an optimized tree with 4 levels of buffers that achieves a delay of 5.1ns.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 3

    ECE152B HW3 Sample solutions 1.

    BUS Zout Zin Xout

    Xin

    Yin

    MUX

    SelA SelB

    MUX

    ALU

    INC RSH ADD SUB

    2. (a)

    Arrival time Required time Slack (b)

    A 2 3 1

    B 5 8 3

    C 3 3 0

    Arrival time Required time Slack

    A 5 7 2

    B 10 13 3

    C 6 6 0

    (c) Tmin= tc-q + longest_delay+ tsu = 12+1+2=15


    3. Considerasynchronouscircuitwith300flipflopsandasingleclocksource.Weare

    interestedindesigningitsclocktree.Assumethatabufferwithzeroloadhasa propagationdelayof0.25ns.Alsoassumethatasignalwithasinglefanout(eitherto aflipfloportoabuffer)hasadelay(duetoanonzeroslewrate)of0.3nsandthe capacitiveloadofeachadditionalfanoutwillcauseanextra0.2nsdelay(duetoa longerslewrate).


    a. Whatisthetotaldelayfromtheclocksourcetoaflipflop'sclockinputifonlyone

    bufferisusedtodriveall300flipflopsintheclocktree. 0.3 ns + 0.25 ns + 1*0.3ns + 299*0.2 ns total delay : 60.65 ns


    b. Whatisthetotaldelayfromtheclocksourcetoaflipflop'sclockinputifbuffers

    areusedtolimitthenumberoffanouts(toflipflopsorbuffers)to8.Showyour clocktreeandthetotaldelayfromthesourcetoaflipflop'sclockinput.(Note: theclocksourcehastobeconnectedtoabufferbeforebeingconnectedtoother buffersorflipflops.)

    0.3 ns + 0.25 ns + 1*0.3 + 7*0.2 ns + 0.25 ns + 1*0.3 + 7*0.2 ns + 0.25 ns + 1*0.3 + 4*0.2 ns total delay : 5.55 ns c.Showaclocktreesolutionthathasaminimumtotaldelayfromtheclocksourcetoa flipflop'sclockinput(Note:Again,theclocksourcehastobeconnectedtoabuffer beforebeingconnectedtootherbuffersorflipflops.) Thesolutionwithminimumdelay:Thefirstlevelofbufferdrives4secondlevelbuffers. Eachsecondlevelbufferdrives4thirdlevelbuffers(sothereare16thirdlevelbuffers). Eachthirdlevelbufferdrives4fourthlevelbuffers(sothereare64fourthlevelbuffers). Eachfourthlevelbufferdrives5flipflops(somemaydrive4flipflops). Thetotaldelayis: 0.3+ 0.25*4+ (1*0.3+3*0.2)*3+ (1*0.3+4*0.2) totaldelay:5.1ns

    [delayof4levelsofbuffers] [interconnectdelaywith4loads=(1*0.3+3*0.2). Thereare3suchinterconnectdelays] [interconnectdelaywith4loads]

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