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Computer Architecture
INSTITUT FR INFORMATIK
COMPUTER ARCHITECTURE
Lecture 17
Input/Output
Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca
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INPUT/OUTPUT
Input/Output problem Secondary memory technology (magnetic, optical) I/O device selection (addressing) I/O protocols Data transfer mechanism Synchronization mechanism
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INPUT/OUTPUT
Historically a neglected subject within computer architecture
Many benchmarks ignore I/O
Cost distribution
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INPUT/OUTPUT PROBLEM
Factors that make interfacing difficult The encoding of the transmitted word must be that which is employed by the I/O device. Operating Rates
The CPU and Main Memory operate at many times the speed of I/O devices
WORD-LENGTH DIFFERENCES
The output "word" must be the correct word length for the output device. Transmission by:
Serial-by-Bit Serial-by-Character (Byte) - (quasiparallel) Serial-by-Word - (parallel) Device 1 Computer or DEVICE 1 Input device 1 2 3 4 1
T1 T2 T3
DEVICE 2
2
T4
4 x
3
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DESIGN
Design depends on Device Operating Speed Device Proximity to Processor
Local Remote
Link Cost
Remote (Communications Cost/Speed)
Control is embedded in message train Parallel: Prevention of Skewing Serial: Clocking and Synchronization
Errors
Factors Prevention
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OPERATING RATES
ERRORS
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COMPONENT AGING
CIRCUIT PARAMETERS DRIFT MECHANICAL WEAR SKEW
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USER MISTAKES
MISSEQUENCING OF PROGRAMS INCORRECT PROCEDURES INCORRECT MOUNTING OF STORAGE MEDIA
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DATA TRANSFER
1 Program controlled I/O addressable buffer register Use normal op-codes Interface
Address Decoding Control Circuits Data Register, Status Register
2 Block transfer of data to Main Memory space. Direct Memory Access (DMA)
Concept is to provide circuitry to transfer data, a word at a time, consistent with the device speed and automatically sequence the transfer using registers in the DMA controller.
4 Connection of DMA (control with memory means memory has to be shared between CPU and I/O devices)
A memory bus controller must be provided to coordinate memory usage Cycle stealing is the process of interweaving I/O priorities between microoperations in the execution of an instruction
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SYNCHRONIZATION POLLING
The CPU must have some means to coordinate its external devices The CPU has to know the status of devices and when events occur Basically two methods are used; Polling (status checking) and interrupts
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INTERRUPTS
General term used in a loose sense for any infrequent or exceptional event that causes a CPU to make a temporary transfer of control from its current program to another program that services the event I/O interrupt are used to:
request CPU to initiate a new I/O operation signal completion of I/O operation signal occurrence of hardware / software errors
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INTERRUPT
A typical interrupt sequence is as follows: The CPU executes a program sequence A special signal, Interrupt Request, is received by the CPU The CPU acknowledges the interrupt and stops execution,(usually after an instruction cycle) of its current program and stores registers in memory (at a minimum the Program Counter (PC) and the Prorgram Status Word (PSW) The CPU's program counter (PC) is set to a new address where an Interrupt Service Routine resides The CPU performs execution as normal
Note: that another interrupt sequence could be initiated while the CPU is performing the service routine Interrupt masks may be set to prevent the latter from occurring
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INTERRUPT (continued)
The CPU may return to the original program sequence when a special return from interrupt (RTI) instruction is executed. In such case the registers saved in Step c are restored and the program counter (PC) address is then held when the interrupt was acknowledged at Step c The concept of an Interrupt is general. Interrupts may be initiated from
Internal operation codes Arithmetic or logical errors External events
Interrupts greatly facilitate operating systems where control needs to be transferred back to the operating system when various events occur Several interrupts may happen within a short period of time and we need methods of handling the interrupts through priority systems
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CPU Channel
1 S AND Channel interrupt flip flop
OR
INTERRUPT HANDLING
There are several types and sources of interrupts They have different priorities Need to screen interrupts
use INTEnable; INTDisable commands
Vectored interrupt: IO device provides address of interrupt service routine (and other information)
Automatically disable other interrupts before starting interrupt service routine
What if interrupting device hangs? Nested interrupts - a higher priority interrupt can be acknowledged and serviced from within the routine of a lower priority interrupt
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CPU
INT REQ 3 INT REQ 2 INT REQ 1 INT REQ 0 IO port 0 IO device A IO port 1 IO port 2 Output device B IO port 3 Input device C
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170
D e v ic e B s e rv ic e ro u tin e
240
D e v ic e C s e rv ic e ro u tin e
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Address decoder
I/O Interface
Control circuit
Input devices
FUNCTIONS (I/O) SELECT I/O DEVICE EXCHANGE "DATA UNITS" WITH DEVICE (DATA TRANSFER) SYNCHRONIZE (COORDINATE) TIMING OF I/O OPERATIONS.
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Device Selector Decoder (AND gate with inverters) Device Command Decoder Logical Decoder to select function
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I/O Channels
Selector (High Speed) Multiplexer (Byte) Block Multiplexers
Channel Programs
Control Words Registers
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I/O
1. 2. 3. 4. 5.
Program controlled Direct Memory Access (DMA) Selector Character Mux (Byte) Block mux (Burst)
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PROGRAMMED I/O
Begin LDA STA LDA STA WAIT TST BPL LDA STA INC BNZ END HALT OSEL 1 SELECT # -10 CNT OSTATUS WAIT CHAR+ OBUFF CNT WAIT DEVICE CODE SELECT DEVICE REGISTER SET COUNT=-10 CHECK OUTPUT STATUS REGISTER, IF STATUS PLUS WAIT STATUS WORD PICK UP CHARACTER, INCREMENT ADDRESS STORE CHARACTER IN OUTPUT BUFFER CNT=CNT+1, -10+1 = -9 ETC. OUTPUT NEXT CHARACTER (BRANCH NON ZERO) END OF OUTPUT
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I/O
1
CPU
MEMORY
I/O
n
I/O BUS
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DMA ACCESS
IO operation initiated by CPU Example: to transfer a block of data, need four instructions:
Load MAR Load word count Read/Write GO
On task completion DMA informs CPU through an interrupt IO operation initiated by I/O device
DMA request sent to CPU Request granted at the next DMA breakpoint
CYCLE STEALING
Both CPU and DMA controller need the system bus to access memory. Who gets priority? DMA block transfer: an entire block is transferred in a single continuous burst
needed for magnetic-disk drives etc. Where data transmission cannot be stopped or slowed down without loss of data supports maximum IO data-transmission rate may starve CPU for relatively long periods
Cycle stealing
DMA steals memory cycles from CPU, transferring one or a few words at a time before returning control Thus memory and CPU bus transactions are interwoven Reduces interference in CPU's activities Reduces I/O transfer rate
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CPU
Word counter
device
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Main memory
Memory bus
CPU
DMA controller
I/O device
I/O device
I/O Bus
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AR IR CPU
DC Control unit
IOAR
IODR
I/O device
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Instruction cycle CPU cycle Fetch instruction Decode instruction Fetch operand Execute instruction Store result
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I/O BUSSES
Control Unit Data Bus Available Status Bus Command Bus Selector Bus
Control Unit
Detect (D)
etc.
Printer 1 Printer 2
To tape units
Disk unit N
Disk unit N
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Channel control
To main memory
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Channel control
to Main Memory
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Main Memory
Central processor
CPU
Multiplexor Channel
Selector Channel
Selector Channel Channel bus IFC H MCS IFC H H H IFC H ... IFC H
IFC L
IFC L
...
IFC M H
IFC
...
IFC MCS L M H
- Interface Controller - Multi Channel Switch - Low-speed device - medium-speed device - High-speed device
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TYPES OF CHANNELS
Selector
- exclusive I/O path for a single High-speed (H) program selected device
Character Multiplexor
- momentary I/O path for a single Medium-speed (M) program selected device (Burst Mode) or - time shared character interleaved path for several Low-speed (L) devices (Byte Mode).
Block Multiplexor
- momentary exclusive path to a single High-speed (H) device (Selector Mode) or - provides a time shared, block interleave path for several High-speed (H) or buffer devices (Multiplex Mode)
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CHARACTER MULTIPLEXOR
Byte Multiplex Mode I/O A B C A B A B A B C C A B C C A B C To Main Memory
C C
B B
C C C C
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INPUT/OUTPUT INSTRUCTIONS
Functions
1. 2. 3. 4. Select a particular device. Specify the first address in memory to or from which data are to be transferred. Specify the number of words which are to be transferred. Select the read or write (R/W) function.
Instructions
EXTERNAL FUNCTION X The contents of address X contains the code for one of the I/O devices which is connected to the I/O register and also a code for the operation to be performed. READ X Transfer the contents of the I/O register to memory location X. CONNECT X This is another form of the external function instruction. If a machine has several channels, this instruction may also specify which channel is used as well as the device to be connected and the function.
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INTR 0
Device 2
Device p
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4 CPU 4 address A lines A 0 1 READ WRITE Control logic Control register Data buffers
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CA IO devices CB
8 8
Bus width (signals) Address/data multiplexed Data width (primary) Transfer size
Future Bus 96 Multiplexed 32 bits Single or multiple Multiple Optional Asynchronous 37.0 MB/sec
IPI 16 N/A 16 bits Single or multiple Single Optional Asynchronous 25.0 MB/sec
SCSI 8 N/A 8 bits Single or multiple Multiple Optional Either 5.0 MB/sec or 1.5 MB/sec 5.0 MB/sec or 1.5 MB/sec
Multiple Number of bus masters Split transaction No Asynchronous Clocking Bandwidth, 0-ns 25.0 MB/sec access memory, single word Bandwidth, 150-ns 12.9 MB/sec access memory, single word
15.5 MB/sec
10.0 MB/sec
25.0 MB/sec
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13.6 MB/sec
20.8 MB/sec
13.5 MB/sec
25.0 MB/sec
21
20
21
The first three were defined originally as CPU-memory buses and the last two as I/O buses. For the CPUmemory buses the bandwidth calculations assume a fully loaded bus and are given to both single-word transfers and block transfers of unlimited length; measurements are shown both ignoring memory latency and assuming 150-ns access time. Bandwidth assumes the average distance of a transfer is on-third of the backplane length. (Data in the first three columns is from Borril [1986]), the Bandwidth for the I/O buses is given as their maximum data transfer rate. There are new bus technologies on the PC-Market nowadays, such as PCI and AGP buses.
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SUMMARY
- matching CPU and I/O speeds remains to be a problem - adding separate CPUs on channels ad devices - remarkable technology advances (e.g., flat screen displays, but a 100 year old keyboard remains to be a popular input device) - I/O remains to be the most expensive part of computer systems
Current challenges - further miniaturization - access to information at any place and time at high speeds (e.g., wearable computers) - development of new I/O devices, new sensors, ...
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