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    Prathamesh Chawan
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    The document discusses MOS transistors, including: - MOS transistors operate as voltage-controlled devices, with a conducting channel between source and drain modulated by the gate voltage. - In nMOS transistors, the majority carriers are electrons and the substrate is p-doped, while in pMOS transistors the majority carriers are holes and the substrate is n-doped. - The transistor has different operating regions depending on the gate bias voltage, including cut-off, linear, and saturated regions which determine how drain current varies with gate and drain voltages.

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    The document discusses MOS transistors, including: - MOS transistors operate as voltage-controlled devices, with a conducting channel between source and drain modulated by the gate voltage. - In nMOS transistors, the majority carriers are electrons and the substrate is p-doped, while in pMOS transistors the majority carriers are holes and the substrate is n-doped. - The transistor has different operating regions depending on the gate bias voltage, including cut-off, linear, and saturated regions which determine how drain current varies with gate and drain voltages.

    Copyright:

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    Download as PDF, TXT or read online from Scribd
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    27 views8 pages

    MOS Theory

    Uploaded by

    Prathamesh Chawan
    The document discusses MOS transistors, including: - MOS transistors operate as voltage-controlled devices, with a conducting channel between source and drain modulated by the gate voltage. - In nMOS transistors, the majority carriers are electrons and the substrate is p-doped, while in pMOS transistors the majority carriers are holes and the substrate is n-doped. - The transistor has different operating regions depending on the gate bias voltage, including cut-off, linear, and saturated regions which determine how drain current varies with gate and drain voltages.

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    Attribution Non-Commercial (BY-NC)
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    of 8

    MOS Transistor Theory

    So far, we have viewed a MOS transistor as an ideal switch (digital operation)


    Reality: less than ideal

    ECE 261

    Krish Chakrabarty

    MOS Transistor Theory


    Study conducting channel between source and drain Modulated by voltage applied to the gate (voltagecontrolled device) nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped)

    ECE 261

    Krish Chakrabarty

    Gate Biasing
    Source n+ Gate SiO2 n+ Drain Vgs=0: no current flows from source to drain (insulated by two reverse biased pn junctions Vgs>0: electric field created across substrate
    Channel

    E p-substrate

    VSS (Gnd) Electrons accumulate under gate: region changes from p-type to n-type Conduction path between source and drain
    ECE 261 Krish Chakrabarty 3

    nMOS Device Behavior Polysilicon gate p-substrate


    Depletion region

    Oxide insulator

    Inversion Region (n-type)

    Depletion region

    Vgs << Vt Accumulation mode

    Vgs = Vt Depletion mode

    Vgs > Vt Inversion mode

    Enhancement-mode transistor: Conducts when gate bias Vgs > Vt Depletion-mode transistor: Conducts when gate bias is zero
    ECE 261 Krish Chakrabarty 4

    Transistor Operating Regions


    Cut-off region: accumulation mode, zero current flow Linear region: Vds <= Vgs-Vt, weak inversion layer, drain current depends on Vgs and Vds Saturated region: Vds > Vgs-Vt, strong inversion layer, drain current independent of Vds

    ECE 261

    Krish Chakrabarty

    Threshold Voltage: Concept


    S + VGS G D

    n+

    n+

    n-channel p-substrate B
    ECE 261 Krish Chakrabarty

    Depletion Region

    Current-Voltage Relations
    S VGS G n+ V(x) + L p-substrate B x VDS D n+ ID

    MOS transistor and its bias conditions


    ECE 261 Krish Chakrabarty 7

    Current-Voltage Relations

    ECE 261

    Krish Chakrabarty

    Current-Voltage Relations
    k n: transconductance of transistor W : width-to-length ratio L As W increases, more carriers available to conduct current As L increases, Vds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow

    ECE 261

    Krish Chakrabarty

    Typical Parameter Values


    n-type p-type k 24 microA/V2 9 microA/V2 Vt 0.8V -0.8V

    Why is k higher for n-type transistors?

    ECE 261

    Krish Chakrabarty

    10

    Transistor in Saturation
    VGS G S n+
    -

    VDS > VGS - VT D


    +

    VGS - VT

    n+

    Channel is pinched off


    ECE 261 Krish Chakrabarty 11

    The Gate Capacitance

    ECE 261

    Krish Chakrabarty

    12

    Diffusion Capacitance

    ECE 261

    Krish Chakrabarty

    13

    Parasitic Resistances
    Polysilicon gate G VGS,eff S RS RD D W LD Drain contact

    Drain

    RS = (LS/W)R + RC RD = (LD/W)R + RC
    ECE 261

    RC: contact resistance R : sheet resistance per square of drain-source diffusion


    Krish Chakrabarty 14

    Body Effect
    Many MOS devices on a common substrate
    Substrate voltage of all devices are normally equal

    But several devices may be connected in series


    Increase in source-to-substrate voltage as we proceed vertically along the chain
    g2 V12 g1 V11 d2 s2 d1 s1 Vsb2 = 0 Vsb1 = 0

    Net effect: slight increase in threshold voltage Vt, Vt2>Vt1

    ECE 261

    Krish Chakrabarty

    15

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