AND GATE Workspace for AND Gate Module andgate1(y,a,b); input a,b; output y; assign y=a&b; end module

Test bench module for AND Gate: Module andgate1tb(); reg a,b; wire y; andgate1 N(a,b,y); initial begin #2 a=0;b=0; #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; $stop; end endmodule

OR GATE Workspace for OR Gate: Module orgate1(a,b,y); input a,b; output y; assign y=a/b; end module

Test bench for OR Gate: Module orgate1tb(); reg a,b; wire y; orgate1 N(a,b,y); initial begin #2 a=0;b=0; #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; $stop; end endmodule