VHDL Skripta

UNIVERZITET U SARAJEVU ELEKTROTEHNIKI FAKULTET SARAJEVO MoE (Masters) studij, II godina Projektovanje sistema na ipu
VHDL Tutorijali
Autor: Odsjek:
Faris Hodi Automatika i elektronika Sarajevo, 2010. godine
VHDL Tutorijali
1.
Tutorijal broj 1: Osnovna kombinatorna kola u VHDLu

Zadatak 1:
Napisati VHDL kod koji opisuje jednostavno logiko kolo sa slike 1.
Slika 1. Jednostavno logiko kolo
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and2b1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and2b1; architecture Behavioral of and2b1 is begin c<=a and not b after 10 ns; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS COMPONENT and2b1 PORT( a : IN std_logic; b : IN std_logic; c : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; CONSTANT period: time:=20 ns; --Outputs SIGNAL c : std_logic; BEGIN uut: and2b1 PORT MAP(
VHDL Tutorijali
a => a, b => b, c => c ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a<='0'; b<='0'; wait for period; assert (c='0') report "Greska 1." severity warning; a<='0'; b<='1'; wait for period; assert (c='0') report "Greska 2." severity warning; a<='1'; b<='0'; wait for period; assert (c='1') report "Greska 3." severity warning; a<='1'; b<='1'; wait for period; assert (c='0') report "Greska 4." severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 2: Na osnovu date tabele istine realizirati logiko kolo koje detektuje broj jedinica na ulazu u kolo, te daje jedan na izlazu ako je broj jedinica vei od 1.
Tabela 1. Tabela istine za detektor ulaznih jedinica
Na osnovu tabele istine moe se zapisati:
y = abc + abc + abc + abc = abc + abc + abc + abc + abc + abc = bc + ac + ab
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VHDL Tutorijali
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity detektor1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; y : out STD_LOGIC); end detektor1; architecture Behavioral of detektor1 is begin y<=(a and b) or (a and c) or (b and c); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT detektor1 PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic := '0'; Constant period: time:=20 ns; --Outputs SIGNAL y : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: detektor1 PORT MAP( a => a, b => b, c => c, y => y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a<='0'; b<='0';
VHDL Tutorijali
c<='0'; wait for period; assert (y='0') report "Greska 1" severity warning; a<='0'; b<='0'; c<='1'; wait for period; assert (y='0') report "Greska 2" severity warning; a<='0'; b<='1'; c<='0'; wait for period; assert (y='0') report "Greska 3" severity warning; a<='0'; b<='1'; c<='1'; wait for period; assert (y='1') report "Greska 4" severity warning; a<='1'; b<='0'; c<='0'; wait for period; assert (y='0') report "Greska 5" severity warning; a<='1'; b<='0'; c<='1'; wait for period; assert (y='1') report "Greska 6" severity warning; a<='1'; b<='1'; c<='0'; wait for period; assert (y='1') report "Greska 7" severity warning; a<='1'; b<='1'; c<='1'; wait for period; assert (y='1') report "Greska 8" severity warning; wait; -- will wait forever END PROCESS; END;
VHDL Tutorijali
Zadatak 3: Za kolo sa slike 2 kreirati VHDL model, napisati tri testna sluaja koja e provjeriti ispravnost rada kola i izvriti simulaciju istog.
Slika 2. Shema jednostavnog kola Tabela 2. Tabela istine za kolo sa slike 2
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AB 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
A'C' 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0
AB+A'C' 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1
(AB+A'C')+D 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1
Y 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0
Na osnovu tabele istine se moe zapisati:
y = abcd + abcd + abcd + abc d = ac d + abd

Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jednostavnokolo is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; y : out STD_LOGIC);
VHDL Tutorijali
end jednostavnokolo; architecture Behavioral of jednostavnokolo is -- Za varijantu 2 nije potrebno definisati signale signal a1,a2,a3: std_logic; begin -- Varijanta 1 a1<=a and b; a2<=(not a) and (not c); a3<=a1 or a2; y<=not(a3 or d); -- Varijanta 2 -y<=(a and not b and not d) or (not a and c and not d); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT jednostavnokolo PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; y : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a SIGNAL b SIGNAL c SIGNAL d : : : : std_logic std_logic std_logic std_logic std_logic; := := := := '0'; '0'; '0'; '0';
--Outputs SIGNAL y : BEGIN
-- Instantiate the Unit Under Test (UUT) uut: jednostavnokolo PORT MAP( a => a, b => b, c => c, d => d, y => y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a<='0';
VHDL Tutorijali
b<='0'; c<='0'; d<='0'; wait for 20 ns; assert (y='0') report "Greska 1" severity warning; a<='0'; b<='0'; c<='0'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 2" severity warning; a<='0'; b<='0'; c<='1'; d<='0'; wait for 20 ns; assert (y='1') report "Greska 3" severity warning; a<='0'; b<='0'; c<='1'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 4" severity warning; a<='0'; b<='1'; c<='0'; d<='0'; wait for 20 ns; assert (y='0') report "Greska 5" severity warning; a<='0'; b<='1'; c<='0'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 6" severity warning; a<='0'; b<='1'; c<='1'; d<='0'; wait for 20 ns; assert (y='1') report "Greska 7" severity warning; a<='0'; b<='1'; c<='1'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 8" severity warning; a<='1'; b<='0'; c<='0'; d<='0'; wait for 20 ns; assert (y='1') report "Greska 9" severity warning; a<='1'; b<='0'; c<='0'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 10" severity warning;
VHDL Tutorijali
a<='1'; b<='0'; c<='1'; d<='0'; wait for 20 ns; assert (y='1') report "Greska 11" severity warning; a<='1'; b<='0'; c<='1'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 12" severity warning; a<='1'; b<='1'; c<='0'; d<='0'; wait for 20 ns; assert (y='0') report "Greska 13" severity warning; a<='1'; b<='1'; c<='0'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 14" severity warning; a<='1'; b<='1'; c<='1'; d<='0'; wait for 20 ns; assert (y='0') report "Greska 15" severity warning; a<='1'; b<='1'; c<='1'; d<='1'; wait for 20 ns; assert (y='0') report "Greska 16" severity warning; wait; -- will wait forever END PROCESS; END;
VHDL Tutorijali
Zadatak 4: Projektovati sklop koji za BCD cifru na ulazu daje njen 9 komplement na izlazu, ija tabela istine je data u tabeli 3. Napisati tri testna sluaja i simulacijom provjeriti ispravnost rada kola.
Tabela 3. Tabela istine za sklop BCDto9k
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BCDto9k is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); end BCDto9k; architecture Behavioral of BCDto9k is begin -- Varijanta 1 -- proces: process(a) -- begin -case a is -when "0000"=> -when "0001"=> -when "0010"=> -when "0011"=> -when "0100"=> -when "0101"=> -when "0110"=> -when "0111"=> -when "1000"=> -when "1001"=> -when others=> -end case;
b<="1001"; b<="1000"; b<="0111"; b<="0110"; b<="0101"; b<="0100"; b<="0011"; b<="0010"; b<="0001"; b<="0000"; b<="XXXX";
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VHDL Tutorijali
-end process proces; a="0000" a="0001" a="0010" a="0011" a="0100" a="0101" a="0110" a="0111" a="1000" a="1001" else else else else else else else else else else
-- Varijanta 2 b<="1001" when "1000" when "0111" when "0110" when "0101" when "0100" when "0011" when "0010" when "0001" when "0000" when "XXXX"; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT BCDto9k PORT( a : IN std_logic_vector(3 downto 0); b : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0'); constant period: time:= 20 ns; --Outputs SIGNAL b : std_logic_vector(3 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: BCDto9k PORT MAP( a => a, b => b ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a<= "0000"; wait for period; assert (b="1001") report "Greska 1" severity warning; a<= "0001"; wait for period; assert (b="1000") report "Greska 2" severity warning; a<= "0010"; wait for period;
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VHDL Tutorijali
assert (b="0111") report "Greska 3" severity warning; a<= "0011"; wait for period; assert (b="0110") report "Greska 4" severity warning; a<= "0100"; wait for period; assert (b="0101") report "Greska 5" severity warning; a<= "0101"; wait for period; assert (b="0100") report "Greska 6" severity warning; a<= "0110"; wait for period; assert (b="0011") report "Greska 7" severity warning; a<= "0111"; wait for period; assert (b="0010") report "Greska 8" severity warning; a<= "1000"; wait for period; assert (b="0001") report "Greska 9" severity warning; a<= "1001"; wait for period; assert (b="0000") report "Greska 10" severity warning; a<= "1111"; wait for period; assert (b="XXXX") report "Greska 11" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 5: Na osnovu tabele istine 4 napisati VHDL kod koji opisuje rad 2 u 1 multipleksera.
Tabela 4. Tabela istine za 2-u-1 multiplekser.
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux2u1 is Port ( I0 : in STD_LOGIC; I1 : in STD_LOGIC; S : in STD_LOGIC; Y : out STD_LOGIC);
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VHDL Tutorijali
end mux2u1; architecture Behavioral of mux2u1 is begin Y<= I0 when S='0' else I1 when S='1' else 'Z'; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mux2u1 PORT( I0 : IN std_logic; I1 : IN std_logic; S : IN std_logic; Y : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I0 : std_logic := '0'; SIGNAL I1 : std_logic := '0'; SIGNAL S : std_logic := '0'; constant period: time := 20 ns; --Outputs SIGNAL Y : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: mux2u1 PORT MAP( I0 => I0, I1 => I1, S => S, Y => Y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I0<='0'; I1<='0'; S<='0'; wait for 20 ns; assert (Y='0') report "Greska 1" severity warning; I0<='1'; I1<='0'; S<='0';
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VHDL Tutorijali
wait for 20 ns; assert (Y='1') report "Greska 2" severity warning; I0<='0'; I1<='1'; S<='0'; wait for 20 ns; assert (Y='0') report "Greska 3" severity warning; I0<='1'; I1<='1'; S<='0'; wait for 20 ns; assert (Y='1') report "Greska 4" severity warning; I0<='0'; I1<='0'; S<='1'; wait for 20 ns; assert (Y='0') report "Greska 5" severity warning; I0<='1'; I1<='0'; S<='1'; wait for 20 ns; assert (Y='0') report "Greska 6" severity warning; I0<='0'; I1<='1'; S<='1'; wait for 20 ns; assert (Y='1') report "Greska 7" severity warning; I0<='1'; I1<='1'; S<='1'; wait for 20 ns; assert (Y='1') report "Greska 8" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 6: Na osnovu tabele istine 5 i blok sheme 4 u 1 multipleksera napisati VHDL kod koji opisuje rad ovog kola. Primjetite da su ulazne/izlazne vrijednosti kod multipleksera trobitne vrijednosti, a signal S dvobitna vrijednost.
Slika 3. Blok shema 4-u-1 multipleksera.
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VHDL Tutorijali
Tabela 5. Tabela istine za 4-u-1 multiplekser.
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4u1 is Port ( U0 : in STD_LOGIC_VECTOR (2 downto 0); U1 : in STD_LOGIC_VECTOR (2 downto 0); U2 : in STD_LOGIC_VECTOR (2 downto 0); U3 : in STD_LOGIC_VECTOR (2 downto 0); S : in STD_LOGIC_VECTOR (1 downto 0); I : out STD_LOGIC_VECTOR (2 downto 0)); end mux4u1; architecture Behavioral of mux4u1 is begin I<=U0 when U1 when U2 when U3 when "ZZZ"; S="00" S="01" S="10" S="11" else else else else
end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mux4u1 PORT( U0 : IN std_logic_vector(2 downto 0); U1 : IN std_logic_vector(2 downto 0); U2 : IN std_logic_vector(2 downto 0); U3 : IN std_logic_vector(2 downto 0); S : IN std_logic_vector(1 downto 0); I : OUT std_logic_vector(2 downto 0) ); END COMPONENT; --Inputs
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VHDL Tutorijali
SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL U0 : std_logic_vector(2 downto 0) := (others=>'0'); U1 : std_logic_vector(2 downto 0) := (others=>'0'); U2 : std_logic_vector(2 downto 0) := (others=>'0'); U3 : std_logic_vector(2 downto 0) := (others=>'0'); S : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs SIGNAL I : std_logic_vector(2 downto 0); constant period: time:=20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: mux4u1 PORT MAP( U0 => U0, U1 => U1, U2 => U2, U3 => U3, S => S, I => I ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; U0<="101"; U1<="110"; U2<="010"; U3<="011"; S<="00"; wait for period; assert (I="101") report "Greska 1" severity warning; S<="01"; wait for period; assert (I="110") report "Greska 2" severity warning; S<="10"; wait for period; assert (I="010") report "Greska 3" severity warning; S<="11"; wait for period; assert (I="011") report "Greska 4" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 7: Napisati VHDL kod etverobitnog 2 u 1 (svaki od ulaza je etverobitna vrijednost) multipleksera i testirati rad ovog kola. Kako je ve realiziran 2 u 1 multiplekser u zadatku 5, ovaj dizajn se moe koristiti za realizaciju etverobitnog 2 u 1 multipleksera na sljedei nain:
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VHDL Tutorijali
Source kod 1: (1 bitni 2 u 1 mux)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux2u1 is Port ( I0 : in STD_LOGIC; I1 : in STD_LOGIC; S : in STD_LOGIC; Y : out STD_LOGIC); end mux2u1; architecture Behavioral of mux2u1 is begin Y<= I0 when S='0' else I1 when S='1' else 'Z'; end Behavioral;
Source kod 2: (etverobitni 2 u 1 mux)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cetverobitnimux2u1 is PORT( I00, I01, I02, I03: IN STD_LOGIC; I10, I11, I12, I13: IN STD_LOGIC; S: IN STD_LOGIC; Y0, Y1, Y2, Y3: OUT STD_LOGIC); end cetverobitnimux2u1; architecture Behavioral of cetverobitnimux2u1 is begin -- I (prva cifra je ulaz na muxu 0 ili 1)(druga cifra broj muxa) -- prvi cetverobitni ulaz I00 I01 I02 I03 -- drugi cetverobitni ulaz I10 I11 I12 I13 -- cetverobitni izlaz Y0 Y1 Y2 Y3 Mux2u1_0: entity work.Mux2u1 PORT MAP (I00, I10, S, Y0); Mux2u1_1: entity work.Mux2u1 PORT MAP (I01, I11, S, Y1); Mux2u1_2: entity work.Mux2u1 PORT MAP (I02, I12, S, Y2); Mux2u1_3: entity work.Mux2u1 PORT MAP (I03, I13, S, Y3); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS
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VHDL Tutorijali
-- Component Declaration for the Unit Under Test (UUT) COMPONENT cetverobitnimux2u1 PORT( I00 : IN std_logic; I01 : IN std_logic; I02 : IN std_logic; I03 : IN std_logic; I10 : IN std_logic; I11 : IN std_logic; I12 : IN std_logic; I13 : IN std_logic; S : IN std_logic; Y0 : OUT std_logic; Y1 : OUT std_logic; Y2 : OUT std_logic; Y3 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I00 SIGNAL I01 SIGNAL I02 SIGNAL I03 SIGNAL I10 SIGNAL I11 SIGNAL I12 SIGNAL I13 SIGNAL S : --Outputs SIGNAL Y0 SIGNAL Y1 SIGNAL Y2 SIGNAL Y3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: cetverobitnimux2u1 PORT MAP( I00 => I00, I01 => I01, I02 => I02, I03 => I03, I10 => I10, I11 => I11, I12 => I12, I13 => I13, S => S, Y0 => Y0, Y1 => Y1, Y2 => Y2, Y3 => Y3 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I00<='0'; I01<='1'; I02<='0'; I03<='1'; I10<='1'; I11<='0'; : : : : : : : : : : : : std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic; std_logic; std_logic; std_logic;
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VHDL Tutorijali
I12<='1'; I13<='0'; S<='1'; wait for 50 ns; assert (Y0='1' and Y1='0' and Y2='1' and Y3='0') report "Greska 1" severity warning; I00<='0'; I01<='1'; I02<='0'; I03<='1'; I10<='1'; I11<='0'; I12<='1'; I13<='0'; S<='0'; wait for 50 ns; assert (Y0='0' and Y1='1' and Y2='0' and Y3='1') report "Greska 2" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 8: Realizirati etverobitni 2 u 1 multiplekser bez pomone komponente 2 u 1 multipleksera realiziranog u zadatku 5. Testirajte ispravnost rada kola. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cetverobitnimux2u1 is Port ( I0 : in STD_LOGIC_VECTOR (3 downto 0); I1 : in STD_LOGIC_VECTOR (3 downto 0); S : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end cetverobitnimux2u1; architecture Behavioral of cetverobitnimux2u1 is begin Y<=I0 when S='0' else I1 when S='1' else "ZZZZ"; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;
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VHDL Tutorijali
ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT cetverobitnimux2u1 PORT( I0 : IN std_logic_vector(3 downto 0); I1 : IN std_logic_vector(3 downto 0); S : IN std_logic; Y : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL S : std_logic := '0'; SIGNAL I0 : std_logic_vector(3 downto 0) := (others=>'0'); SIGNAL I1 : std_logic_vector(3 downto 0) := (others=>'0'); --Outputs SIGNAL Y : BEGIN -- Instantiate the Unit Under Test (UUT) uut: cetverobitnimux2u1 PORT MAP( I0 => I0, I1 => I1, S => S, Y => Y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I0<="0101"; I1<="1010"; S<='1'; wait for 50 ns; assert (Y="1010") report "Greska 1" severity warning; S<='0'; wait for 50 ns; assert (Y="0101") report "Greska 2" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END; std_logic_vector(3 downto 0);
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VHDL Tutorijali
Zadatak 9: U VHDLu realizirati kolo dato na slici 4. Testirajte ispravnost rada kola.
Slika 4. Dijagram kola Tabela 6. Tabela istine za kolo sa slike 4
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
S0 0 1 0 1 0 1 0 1
Izlaz iz AND2 0 0 1 1 0 0 0 0
Izlaz iz M2_1 101 010 101 010 101 010 101 010
Y 101 010 001 001 101 010 101 010
Source kod 1: (trobitni 2 u 1 mux)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux2u1 is Port ( I0 : in STD_LOGIC_VECTOR (2 downto 0); I1 : in STD_LOGIC_VECTOR (2 downto 0); S : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (2 downto 0)); end mux2u1; architecture Behavioral of mux2u1 is begin Y<= I0 when S='0' else I1 when S='1' else "ZZZ"; end Behavioral;
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VHDL Tutorijali
Source kod 2: (kolo sa slike 4)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity zadatak8 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; S0 : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (2 downto 0)); end zadatak8; architecture Behavioral of zadatak8 is component mux2u1 is Port ( I0 : in STD_LOGIC_VECTOR (2 downto 0); I1 : in STD_LOGIC_VECTOR (2 downto 0); S : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (2 downto 0)); end component; signal D0: STD_LOGIC_VECTOR (2 downto 0); signal outand2: STD_LOGIC; begin outand2<=not A and B; M2_1: mux2u1 port map("101","010",S0,D0); M2_2: mux2u1 port map(D0,"001",outand2,Y); end Behavioral
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT zadatak8 PORT( A : IN std_logic; B : IN std_logic; S0 : IN std_logic; Y : OUT std_logic_vector(2 downto 0) ); END COMPONENT; --Inputs SIGNAL A : std_logic := '0'; SIGNAL B : std_logic := '0'; SIGNAL S0 : std_logic := '0'; --Outputs SIGNAL Y : BEGIN std_logic_vector(2 downto 0);
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VHDL Tutorijali
-- Instantiate the Unit Under Test (UUT) uut: zadatak8 PORT MAP( A => A, B => B, S0 => S0, Y => Y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; A<='0'; B<='0'; S0<='0'; wait for 50 ns; assert(Y="101") report "Greska 1" severity warning; A<='0'; B<='0'; S0<='1'; wait for 50 ns; assert(Y="010") report "Greska 2" severity warning; A<='0'; B<='1'; S0<='0'; wait for 50 ns; assert(Y="001") report "Greska 3" severity warning; A<='0'; B<='1'; S0<='1'; wait for 50 ns; assert(Y="001") report "Greska 4" severity warning; A<='1'; B<='0'; S0<='0'; wait for 50 ns; assert(Y="101") report "Greska 5" severity warning; A<='1'; B<='0'; S0<='1'; wait for 50 ns; assert(Y="010") report "Greska 6" severity warning; A<='1'; B<='1'; S0<='0'; wait for 50 ns; assert(Y="101") report "Greska 7" severity warning; A<='1'; B<='1'; S0<='1'; wait for 50 ns; assert(Y="010") report "Greska 8" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
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VHDL Tutorijali
2.
Tutorijal broj 2: Kombinacione komponente

Zadatak 1:
Na osnovu tabele istine 7 napisati VHDL kod koji opisuje rad 1 u 4 demultipleksera.
Tabela 7. Tabela istine za 1-u-4 demultiplekser.
Source kod (varijanta 1):

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux1u4 Port ( S : I : Y : end dmux1u4; is in STD_LOGIC_VECTOR (1 downto 0); in STD_LOGIC; out STD_LOGIC_VECTOR (3 downto 0));
architecture Behavioral of dmux1u4 is begin Y<=I & "000" when S="00" else '0' & I & "00" when S="01" else "00" & I & '0' when S="10" else "000" & I; end Behavioral;
Test kod (varijanta 1):

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dmux1u4 PORT( S : IN std_logic_vector(1 downto 0); I : IN std_logic; Y : OUT std_logic_vector(3 downto 0) );
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VHDL Tutorijali
END COMPONENT; --Inputs SIGNAL I : SIGNAL S : --Outputs SIGNAL Y : BEGIN -- Instantiate the Unit Under Test (UUT) uut: dmux1u4 PORT MAP( S => S, I => I, Y => Y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I<='1'; S<="00"; wait for 30 ns; assert (Y="1000") report "Greska 1" severity warning; S<="01"; wait for 30 ns; assert (Y="0100") report "Greska 2" severity warning; S<="10"; wait for 30 ns; assert (Y="0010") report "Greska 3" severity warning; S<="11"; wait for 30 ns; assert (Y="0001") report "Greska 4" severity warning; wait; -- will wait forever END PROCESS; END; std_logic := '0'; std_logic_vector(1 downto 0) := (others=>'0'); std_logic_vector(3 downto 0);

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux1u4 is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); Y0 : out STD_LOGIC; Y1 : out STD_LOGIC; Y2 : out STD_LOGIC; Y3 : out STD_LOGIC); end dmux1u4; architecture Behavioral of dmux1u4 is begin PROCESS(I, S) BEGIN IF S="00" THEN Y0<=I; Y1<='0'; Y2<='0'; Y3<='0';
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VHDL Tutorijali
ELSIF S="01" THEN Y0<='0'; Y1 <=I; Y2<='0'; Y3<='0'; ELSIF S="10" THEN Y0<='0'; Y1 <='0'; Y2<=I; Y3<='0'; ELSIF S="11" THEN Y0<='0'; Y1 <='0'; Y2<='0'; Y3<= I; END IF; END PROCESS; end Behavioral;

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dmux1u4 PORT( I : IN std_logic; S : IN std_logic_vector(1 downto 0); Y0 : OUT std_logic; Y1 : OUT std_logic; Y2 : OUT std_logic; Y3 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I : SIGNAL S : --Outputs SIGNAL Y0 SIGNAL Y1 SIGNAL Y2 SIGNAL Y3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: dmux1u4 PORT MAP( I => I, S => S, Y0 => Y0, Y1 => Y1, Y2 => Y2, Y3 => Y3 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I<='1'; S<="00"; wait for 10 ns; wait I <= S <= wait for 100ns; '0'; "01"; for 10 ns; : : : : std_logic := '0'; std_logic_vector(1 downto 0) := (others=>'0'); std_logic; std_logic; std_logic; std_logic;
assert (Y0='1' and Y1='0' and Y2='0' and Y3='0') report "Greska 1!" severity warning;
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VHDL Tutorijali
wait I <= S <= wait wait I <= S <= wait wait I <= S <= wait wait I <= S <= wait
for 100ns; '1'; "10"; for 10 ns; for 100ns; '1'; "11"; for 10 ns; for 100ns; '0'; "11"; for 10 ns; for 100ns; '0'; "01"; for 10 ns;
wait; -- will wait forever END PROCESS; END;
Zadatak 2: Realizirati etvorobitni 1 u 4 demultiplekser (sa ili bez koritenja dizajna iz Zadatka 1.). Testirati ispravnost rada kola. Source kod 1 (varijanta 1): (jednobitni 1 u 4 dmux)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux1u4 is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC; Y0 : out STD_LOGIC; Y1 : out STD_LOGIC; Y2 : out STD_LOGIC; Y3 : out STD_LOGIC); end dmux1u4; architecture Behavioral of dmux1u4 is begin process(I, S) begin if S="00" then y0<=I; y1<='0'; y2<='0'; elsif S="01" then y0<='0'; y1<=I; y2<='0'; elsif S="10" then y0<='0'; y1<='0'; y2<=I; elsif S="11" then y0<='0'; y1<='0'; y2<='0'; else y0<='Z'; y1<='Z'; y2<='Z'; y3<='Z'; end if; end process; end Behavioral; y3<='0'; y3<='0'; y3<='0'; y3<=I;
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VHDL Tutorijali
Source kod 2 (varijanta 1):

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cetverobitnidmux1u4 is Port ( I0 : in STD_LOGIC; I1 : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); Y00 : out STD_LOGIC; Y01 : out STD_LOGIC; y02 : out STD_LOGIC; y03 : out STD_LOGIC; y10 : out STD_LOGIC; y11 : out STD_LOGIC; y12 : out STD_LOGIC; y13 : out STD_LOGIC; y20 : out STD_LOGIC; y21 : out STD_LOGIC; y22 : out STD_LOGIC; y23 : out STD_LOGIC; y30 : out STD_LOGIC; y31 : out STD_LOGIC; y32 : out STD_LOGIC; y33 : out STD_LOGIC); end cetverobitnidmux1u4; architecture Behavioral of cetverobitnidmux1u4 is component dmux1u4 is port ( S: in std_logic_vector (1 downto 0); I: in std_logic; y0: out std_logic; y1: out std_logic; y2: out std_logic; y3: out std_logic); end component; begin dmux1: dmux1u4 dmux2: dmux1u4 dmux3: dmux1u4 dmux4: dmux1u4 end Behavioral; port port port port map map map map (I0, (I1, (I2, (I3, S, S, S, S, y00, y10, y20, y30, y01, y11, y21, y31, y02, y12, y22, y32, y03); y13); y23); y33);

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT cetverobitnidmux1u4 PORT(
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VHDL Tutorijali
I0 : IN std_logic; I1 : IN std_logic; I2 : IN std_logic; I3 : IN std_logic; S : IN std_logic_vector(1 downto 0); Y00 : OUT std_logic; Y01 : OUT std_logic; y02 : OUT std_logic; y03 : OUT std_logic; y10 : OUT std_logic; y11 : OUT std_logic; y12 : OUT std_logic; y13 : OUT std_logic; y20 : OUT std_logic; y21 : OUT std_logic; y22 : OUT std_logic; y23 : OUT std_logic; y30 : OUT std_logic; y31 : OUT std_logic; y32 : OUT std_logic; y33 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I0 : std_logic := '0'; SIGNAL I1 : std_logic := '0'; SIGNAL I2 : std_logic := '0'; SIGNAL I3 : std_logic := '0'; SIGNAL S : std_logic_vector(1 downto 0) := (others=>'0'); --Outputs SIGNAL Y00 SIGNAL Y01 SIGNAL y02 SIGNAL y03 SIGNAL y10 SIGNAL y11 SIGNAL y12 SIGNAL y13 SIGNAL y20 SIGNAL y21 SIGNAL y22 SIGNAL y23 SIGNAL y30 SIGNAL y31 SIGNAL y32 SIGNAL y33 BEGIN -- Instantiate the Unit Under Test (UUT) uut: cetverobitnidmux1u4 PORT MAP( I0 => I0, I1 => I1, I2 => I2, I3 => I3, S => S, Y00 => Y00, Y01 => Y01, y02 => y02, y03 => y03, y10 => y10, y11 => y11, y12 => y12, y13 => y13, y20 => y20, y21 => y21, : : : : : : : : : : : : : : : : std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic;
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VHDL Tutorijali
y22 y23 y30 y31 y32 y33 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here I0 <= '1'; I1 <= '0'; I2 <= '0'; I3 <= '1'; S <= "00"; wait for 50 ns; S <= "01"; wait for 50 ns; S <= "10"; wait for 50 ns; S <= "11"; wait; -- will wait forever END PROCESS; END; => => => => => => y22, y23, y30, y31, y32, y33

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity zadatak1 is Port ( I : in STD_LOGIC_VECTOR (3 downto 0); S : in STD_LOGIC_VECTOR (1 downto 0); Y0 : out STD_LOGIC_VECTOR (3 downto 0); Y1 : out STD_LOGIC_VECTOR (3 downto 0); Y2 : out STD_LOGIC_VECTOR (3 downto 0); Y3 : out STD_LOGIC_VECTOR (3 downto 0)); end zadatak1; architecture Behavioral of zadatak1 is begin Y0<=I when S="00" "0000"; Y1<=I when S="01" "0000"; Y2<=I when S="10" "0000"; Y3<=I when S="11" "0000"; end Behavioral; else else else else
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VHDL Tutorijali

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT zadatak1 PORT( I : IN std_logic_vector(3 downto 0); S : IN std_logic_vector(1 downto 0); Y0 : OUT std_logic_vector(3 downto 0); Y1 : OUT std_logic_vector(3 downto 0); Y2 : OUT std_logic_vector(3 downto 0); Y3 : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL I : SIGNAL S : --Outputs SIGNAL Y0 SIGNAL Y1 SIGNAL Y2 SIGNAL Y3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: zadatak1 PORT MAP( I => I, S => S, Y0 => Y0, Y1 => Y1, Y2 => Y2, Y3 => Y3 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I<="1010"; S<="00"; wait for 10 ns; assert(Y0=I and Y1="0000" and Y2="0000" and Y3="0000") report "E1" severity warning; wait for 100 ns; S<="01"; wait for 10 ns; assert(Y1=I and Y0="0000" and Y2="0000" and Y3="0000") report "E1" severity warning; wait for 100 ns; S<="10"; wait for 10 ns; : : : : std_logic_vector(3 downto 0) := (others=>'0'); std_logic_vector(1 downto 0) := (others=>'0'); std_logic_vector(3 std_logic_vector(3 std_logic_vector(3 std_logic_vector(3 downto downto downto downto 0); 0); 0); 0);
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VHDL Tutorijali
assert(Y2=I and Y1="0000" and Y0="0000" and Y3="0000") report "E1" severity warning; wait for 100 ns; S<="11"; wait for 10 ns; assert(Y3=I and Y1="0000" and Y2="0000" and Y0="0000") report "E1" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 3: Realizirati 4 u 2 koder ija tabela istine je data u tabeli 8. Testirati ispravnost rada kola.
Tabela 8. Skraena tabela istine za 4 u 2 koder
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity koder4u2 is Port ( I3 : in I2 : in I1 : in I0 : in A : out B : out end koder4u2; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);
architecture Behavioral of koder4u2 is begin A<=I3 or I2; B<=I3 or I1; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS
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VHDL Tutorijali
END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT koder4u2 PORT( I3 : IN std_logic; I2 : IN std_logic; I1 : IN std_logic; I0 : IN std_logic; A : OUT std_logic; B : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I3 SIGNAL I2 SIGNAL I1 SIGNAL I0 --Outputs SIGNAL A : SIGNAL B : BEGIN -- Instantiate the Unit Under Test (UUT) uut: koder4u2 PORT MAP( I3 => I3, I2 => I2, I1 => I1, I0 => I0, A => A, B => B ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I3<='0'; I2<='0'; I1<='0'; I0<='1'; wait for 10 ns; assert (A='0' and B='0') report "Greska 1" severity warning; wait for 100 ns; I3<='0'; I2<='0'; I1<='1'; I0<='0'; wait for 10 ns; assert (A='0' and B='1') report "Greska 2" severity warning; wait for 100 ns; I3<='0'; I2<='1'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='1' and B='0') report "Greska 3" severity warning; wait for 100 ns; I3<='1'; : : : : std_logic std_logic std_logic std_logic std_logic; std_logic; := := := := '0'; '0'; '0'; '0';
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VHDL Tutorijali
I2<='0'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='1' and B='1') report "Greska 4" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 4: Realizirati 4 u 2 prioretni koder ija skraena tabela istine je data u tabeli 9, kao i potpuna tabela istine 10 koja definie izlaze za sve ulaze u kolo. Testirati ispravnost rada kola za proizvoljan broj sluaja.
Tabela 9. Skraena tabela istine za 4-u-2 prioretni koder
Tabela 10. Potpuna tabela istine za 4-u-2 prioretni koder
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VHDL Tutorijali
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prioretnikoder4u2 is Port ( I3 : in STD_LOGIC; I2 : in STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC; A : out STD_LOGIC; B : out STD_LOGIC; Y : out STD_LOGIC); end prioretnikoder4u2; architecture Behavioral of prioretnikoder4u2 is begin A<=I2 or I3; B<=I3 or (not I2 and I1); Y<=not I3 and not I2 and not I1 and not I0; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT prioretnikoder4u2 PORT( I3 : IN std_logic; I2 : IN std_logic; I1 : IN std_logic; I0 : IN std_logic; A : OUT std_logic; B : OUT std_logic; Y : OUT std_logic ); END COMPONENT; --Inputs SIGNAL I3 SIGNAL I2 SIGNAL I1 SIGNAL I0 --Outputs SIGNAL A : SIGNAL B : SIGNAL Y : BEGIN : : : : std_logic std_logic std_logic std_logic std_logic; std_logic; std_logic; := := := := '0'; '0'; '0'; '0';
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VHDL Tutorijali
-- Instantiate the Unit Under Test (UUT) uut: prioretnikoder4u2 PORT MAP( I3 => I3, I2 => I2, I1 => I1, I0 => I0, A => A, B => B, Y => Y ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; I3<='0'; I2<='0'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='0' and B='0' and Y='1') report "Greska 1" severity warning; wait for 100 ns; I3<='0'; I2<='0'; I1<='0'; I0<='1'; wait for 10 ns; assert (A='0' and B='0' and Y='0') report "Greska 2" severity warning; wait for 100 ns; I3<='0'; I2<='0'; I1<='1'; I0<='0'; wait for 10 ns; assert (A='0' and B='1' and Y='0') report "Greska 3" severity warning; wait for 100 ns; I3<='0'; I2<='0'; I1<='1'; I0<='1'; wait for 10 ns; assert (A='0' and B='1' and Y='0') report "Greska 4" severity warning; wait for 100 ns; I3<='0'; I2<='1'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='1' and B='0' and Y='0') report "Greska 5" severity warning; wait for 100 ns; I3<='0'; I2<='1'; I1<='0'; I0<='1'; wait for 10 ns; assert (A='1' and B='0' and Y='0') report "Greska 6" severity warning; wait for 100 ns; I3<='0'; I2<='1'; I1<='1'; I0<='0';
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VHDL Tutorijali
wait for 10 ns; assert (A='1' and B='0' and Y='0') report "Greska 7" severity warning; wait for 100 ns; I3<='0'; I2<='1'; I1<='1'; I0<='1'; wait for 10 ns; assert (A='1' and B='0' and Y='0') report "Greska 8" severity warning; wait for 100 ns; I3<='1'; I2<='0'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 9" severity warning; wait for 100 ns; I3<='1'; I2<='0'; I1<='0'; I0<='1'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 10" severity warning; wait for 100 ns; I3<='1'; I2<='0'; I1<='1'; I0<='0'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 11" severity warning; wait for 100 ns; I3<='1'; I2<='0'; I1<='1'; I0<='1'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 12" severity warning; wait for 100 ns; I3<='1'; I2<='1'; I1<='0'; I0<='0'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 13" severity warning; wait for 100 ns; I3<='1'; I2<='1'; I1<='0'; I0<='1'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 14" severity warning; wait for 100 ns; I3<='1'; I2<='1'; I1<='1'; I0<='0'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 15" severity warning; wait for 100 ns;
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VHDL Tutorijali
I3<='1'; I2<='1'; I1<='1'; I0<='1'; wait for 10 ns; assert (A='1' and B='1' and Y='0') report "Greska 16" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 5: Realizirati 2 u 4 dekoder ija tabela istine je data u tabeli 11. Provjeriti ispravnost rada kola.
Tabela 11. Tabela istine za 2-u-4 dekoder
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dekoder2u4 is Port ( E : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; I0 : out STD_LOGIC; I1 : out STD_LOGIC; I2 : out STD_LOGIC; I3 : out STD_LOGIC); end dekoder2u4; architecture Behavioral of dekoder2u4 is begin I0<=E I1<=E I2<=E I3<=E or or or or A or B; A or not B; not A or B; not A or not B;
end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
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VHDL Tutorijali
USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dekoder2u4 PORT( E : IN std_logic; A : IN std_logic; B : IN std_logic; I0 : OUT std_logic; I1 : OUT std_logic; I2 : OUT std_logic; I3 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL E : SIGNAL A : SIGNAL B : --Outputs SIGNAL I0 SIGNAL I1 SIGNAL I2 SIGNAL I3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: dekoder2u4 PORT MAP( E => E, A => A, B => B, I0 => I0, I1 => I1, I2 => I2, I3 => I3 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; E<='1'; A<='X'; B<='X'; wait for 10 ns;
assert(I0='1' and I1='1' and I2='1' and I3='1') report "Greska 1" severity warning;
std_logic := '0'; std_logic := '0'; std_logic := '0'; : : : : std_logic; std_logic; std_logic; std_logic;
wait for 100 ns; E<='0'; A<='0'; B<='0'; wait for 10 ns; wait for 100 ns; E<='0'; A<='0'; B<='1'; wait for 10 ns;
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VHDL Tutorijali
wait for 100 ns; E<='0'; A<='1'; B<='0'; wait for 10 ns; wait for 100 ns; E<='0'; A<='1'; B<='1'; wait for 10 ns;
-- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 6: Realizirati 23 x 32 ROM modul koji ima 8 ulaznih adresnih linija, od kojih svaka sadri 32 bita informacije. Provjeriti ispravnost rada kola. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ROM8x32 is Port ( adresa : in STD_LOGIC_VECTOR (2 downto 0); podaci : out STD_LOGIC_VECTOR (31 downto 0)); end ROM8x32; architecture Behavioral of ROM8x32 is TYPE ROMTabela is ARRAY (0 to 7) of STD_LOGIC_VECTOR (31 downto 0); constant ROMPodaci: ROMTabela := ( x"70000000", x"0E000000", x"01C00000", x"00380000", x"00070000", x"0000E000", x"00001C00", x"00000380" ); begin process (adresa) begin podaci<=ROMpodaci(conv_integer(adresa)); -- konvertuje se trobitna adresa u cijeli broj end process; end Behavioral;
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Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ROM8x32 PORT( adresa : IN std_logic_vector(2 downto 0); podaci : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs SIGNAL adresa : --Outputs SIGNAL podaci : BEGIN -- Instantiate the Unit Under Test (UUT) uut: ROM8x32 PORT MAP( adresa => adresa, podaci => podaci ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 50 ns; adresa<="000"; wait for 10 ns; assert(podaci=x"70000000") report "Greska 1" severity warning; wait for 50 ns; adresa<="001"; wait for 10 ns; assert(podaci=x"0E000000") report "Greska 2" severity warning; wait for 50 ns; adresa<="010"; wait for 10 ns; assert(podaci=x"01C00000") report "Greska 3" severity warning; wait for 50 ns; adresa<="011"; wait for 10 ns; assert(podaci=x"00380000") report "Greska 4" std_logic_vector(2 downto 0) := (others=>'0'); std_logic_vector(31 downto 0);
severity warning;
wait for 50 ns; adresa<="100"; wait for 10 ns; assert(podaci=x"00070000") report "Greska 5" severity warning; wait for 50 ns; adresa<="101";
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VHDL Tutorijali
wait for 10 ns; assert(podaci=x"0000E000") report "Greska 6" severity warning; wait for 50 ns; adresa<="110"; wait for 10 ns; assert(podaci=x"00001C00") report "Greska 7" severity warning; wait for 50 ns; adresa<="111"; wait for 10 ns; assert(podaci=x"00000380") report "Greska 8" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 7: Funkcionalnost polusumatora opisana je tabelom istine 12., a blok shema data je na slici 5. Napisati VHDL kod koji opisuje polusumator.
Slika 5. Blok shema polusumatora Tabela 11. Tabela istine za jednobitni polusumator.
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity polusumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; S : out STD_LOGIC; C : out STD_LOGIC); end polusumator; architecture Behavioral of polusumator is begin S<=A xor B; C<=A and B; end Behavioral;
Test kod:
LIBRARY ieee;
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VHDL Tutorijali
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT polusumator PORT( A : IN std_logic; B : IN std_logic; S : OUT std_logic; C : OUT std_logic ); END COMPONENT; --Inputs SIGNAL A : SIGNAL B : --Outputs SIGNAL S : SIGNAL C : BEGIN -- Instantiate the Unit Under Test (UUT) uut: polusumator PORT MAP( A => A, B => B, S => S, C => C ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; A<='0'; B<='0'; wait for 10 ns; assert(S='0' and C='0') report "Greska " severity warning; wait for 100 ns; A<='0'; B<='1'; wait for 10 ns; assert(S='1' and C='0') report "Greska " severity warning; wait for 100 ns; A<='1'; B<='0'; wait for 10 ns; assert(S='1' and C='0') report "Greska " severity warning; wait for 100 ns; A<='1'; B<='1'; wait for 10 ns; assert(S='0' and C='1') report "Greska " severity warning; wait; -- will wait forever END PROCESS; std_logic := '0'; std_logic := '0'; std_logic; std_logic;
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VHDL Tutorijali
END;
Zadatak 8: Data je blok shema punog sumatora, kao i tabela istine koja opisuje njegov rad. Napisati VHDL kod koji opisuje funkcionalnost datog kola. Napisati nekoliko testnih sluajeva koja e pokazati da kolo radi ispravno.
Slika 6. Blok shema punog sumatora Tabela 12. Tabela istine za jednobitni puni sumator
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity punisumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end punisumator; architecture Behavioral of punisumator is begin S<=Cin xor A xor B; Cout<=(Cin and A)or(Cin and B)or(A and B); end Behavioral;
Test kod:
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VHDL Tutorijali
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT punisumator PORT( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; S : OUT std_logic; Cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL A : std_logic := '0'; SIGNAL B : std_logic := '0'; SIGNAL Cin : std_logic := '0'; --Outputs SIGNAL S : std_logic; SIGNAL Cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: punisumator PORT MAP( A => A, B => B, Cin => Cin, S => S, Cout => Cout ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 50 ns; Cin<='0'; A<='0'; B<='0'; wait for 10 ns; assert(S='0' and Cout='0') report "Greska 1" severity warning; wait for 50 ns; Cin<='0'; A<='0'; B<='1'; wait for 10 ns; assert(S='1' and Cout='0') report "Greska 2" severity warning; wait for 50 ns; Cin<='0'; A<='1'; B<='0'; wait for 10 ns; assert(S='1' and Cout='0') report "Greska 3" severity warning; wait for 50 ns; Cin<='0';
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VHDL Tutorijali
A<='1'; B<='1'; wait for 10 ns; assert(S='0' and Cout='1') report "Greska 4" severity warning; wait for 50 ns; Cin<='1'; A<='0'; B<='0'; wait for 10 ns; assert(S='1' and Cout='0') report "Greska 5" severity warning; wait for 50 ns; Cin<='1'; A<='0'; B<='1'; wait for 10 ns; assert(S='0' and Cout='1') report "Greska 6" severity warning; wait for 50 ns; Cin<='1'; A<='1'; B<='0'; wait for 10 ns; assert(S='0' and Cout='1') report "Greska 7" severity warning; wait for 50 ns; Cin<='1'; A<='1'; B<='1'; wait for 10 ns; assert(S='1' and Cout='1') report "Greska 8" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 9: Cilj ovog zadatka je da se iskoristi dizajn jednobitnog punog sabiraa za realizaciju etverobitnog sabiraa. Blok shema etverobitnog punog sabiraa data je na slici 7.
Slika 7. Blok shema etverobitnog punog sabiraa
Source kod 1: (puni sabira)
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VHDL Tutorijali
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity punisumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end punisumator; architecture Behavioral of punisumator is begin S<=Cin xor A xor B; Cout<=(Cin and A)or(Cin and B)or(A and B); end Behavioral;
Source kod 2: (etverobitni puni sabira)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cetverobitnisabirac is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC); end cetverobitnisabirac; architecture Behavioral of cetverobitnisabirac is component punisumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end component; signal c0, c1,c2: STD_LOGIC; begin FA0: punisumator FA1: punisumator FA2: punisumator FA3: punisumator end Behavioral; port port port port map map map map (Cin, (c0, (c1, (c2, A(0), A(1), A(2), A(3), B(0), B(1), B(2), B(3), S(0), S(1), S(2), S(3), c0); c1); c2); Cout);
Test kod:
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VHDL Tutorijali
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT cetverobitnisabirac PORT( A : IN std_logic_vector(3 downto 0); B : IN std_logic_vector(3 downto 0); Cin : IN std_logic; S : OUT std_logic_vector(3 downto 0); Cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL Cin : std_logic := '0'; SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0'); SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0'); --Outputs SIGNAL S : std_logic_vector(3 downto 0); SIGNAL Cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: cetverobitnisabirac PORT MAP( A => A, B => B, Cin => Cin, S => S, Cout => Cout ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; A<="0100"; B<="0010"; Cin<='0'; wait for 10 ns; assert(S="0110" and Cout='0') report "Greska 1" severity warning; wait for 100 ns; A<="1000"; B<="1010"; Cin<='0'; wait for 10 ns; assert(S="0010" and Cout='1') report "Greska 2" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 10: 48
VHDL Tutorijali
(Barel ifter - rotiranje u lijevo bez gubitka podataka) Na osnovu date tabele istine 13. realizirati barel ifter koji rotira bite u lijevo, bez gubitka podataka. Provjeriti ispravnost rada kola.
Tabela 13. Tabela istine barel iftera sa rotiranjem u lijevo.
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity barelnalijevo is Port ( D : in BIT_VECTOR (7 downto 0); S : in STD_LOGIC_VECTOR (2 downto 0); Q : out BIT_VECTOR (7 downto 0)); end barelnalijevo; architecture Behavioral of barelnalijevo is begin -- Y<= Q rol N kruzni pomak ulijevo za N bita Q<= D rol conv_integer(S); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use std.textio.all; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT barelnalijevo PORT( D : IN bit_vector(7 downto 0); S : IN std_logic_vector(2 downto 0); Q : OUT bit_vector(7 downto 0)
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); END COMPONENT; --Inputs SIGNAL D : SIGNAL S : --Outputs SIGNAL Q : BEGIN -- Instantiate the Unit Under Test (UUT) uut: barelnalijevo PORT MAP( Q => Q, S => S, D => D ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; D<="10010110"; S<="000"; wait for 50 ns; assert(Q="10010110") report "Greska 1" severity warning; S<="001"; wait for 20 ns; assert(Q="00101101") report "Greska 2" severity warning; S<="010"; wait for 50 ns; assert(Q="01011010") report "Greska 3" severity warning; S<="011"; wait for 50 ns; assert(Q="10110100") report "Greska 4" severity warning; S<="100"; wait for 50 ns; assert(Q="01101001") report "Greska 5" severity warning; S<="101"; wait for 50 ns; assert(Q="11010010") report "Greska 6" severity warning; S<="110"; wait for 50 ns; assert(Q="10100101") report "Greska 7" severity warning; S<="111"; wait for 50 ns; assert(Q="01001011") report "Greska 8" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END; bit_vector(7 downto 0) := (others=>'0'); std_logic_vector(2 downto 0) := (others=>'0'); bit_vector(7 downto 0);
Zadatak 11: 50
VHDL Tutorijali
(Barel ifter - rotiranje u lijevo sa gubitkom podataka) Na osnovu date tabele istine 14. realizirati barel ifter koji rotira bite u lijevo sa gubitkom podataka pomou osam 8 u 1 multipleksera. Provjeriti ispravnost rada kola.
Tabela 14. Tabela istine barel iftera sa rotiranjem u lijevo sa gubitkom podataka.
Povezivanje multipleksera:
Tabela 15. Povezivanje 8 u 1 multipleksera CH 0 MUX_7 (izlaz Q7) MUX_6 (izlaz Q6) MUX_5 (izlaz Q5) MUX_4 (izlaz Q4) MUX_3 (izlaz Q3) MUX_2 (izlaz Q2) MUX_1 (izlaz Q1) MUX_0 (izlaz Q0) D7 D6 D5 D4 D3 D2 D1 D0 CH 1 D6 D5 D4 D3 D2 D1 D0 0 CH 2 D5 D4 D3 D2 D1 D0 0 0 CH 3 D4 D3 D2 D1 D0 0 0 0 CH 4 D3 D2 D1 D0 0 0 0 0 CH 5 D2 D1 D0 0 0 0 0 0 CH 6 D1 D0 0 0 0 0 0 0 CH 7 D0 0 0 0 0 0 0 0
Source kod 1: (8 u 1 mux)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8u1 is Port ( CH0 : in STD_LOGIC; CH1 : in STD_LOGIC; CH2 : in STD_LOGIC; CH3 : in STD_LOGIC; CH4 : in STD_LOGIC; CH5 : in STD_LOGIC; CH6 : in STD_LOGIC; CH7 : in STD_LOGIC; S0 : in STD_LOGIC;
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VHDL Tutorijali
S1 : in S2 : in Q : out end mux8u1; architecture Behavioral of mux8u1 is begin Q<= CH0 when CH1 when CH2 when CH3 when CH4 when CH5 when CH6 when CH7 when 'Z'; end Behavioral; S2='0' S2='0' S2='0' S2='0' S2='1' S2='1' S2='1' S2='1' and and and and and and and and S1='0' S1='0' S1='1' S1='1' S1='0' S1='0' S1='1' S1='1' and and and and and and and and S0='0' S0='1' S0='0' S0='1' S0='0' S0='1' S0='0' S0='1' else else else else else else else else STD_LOGIC; STD_LOGIC; STD_LOGIC);
Source kod 2: (Barel ifter sa gubljenjem podataka)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity barelsaupisomnula is Port ( D : in STD_LOGIC_VECTOR (7 downto 0); S : in STD_LOGIC_VECTOR (2 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0)); end barelsaupisomnula; architecture Behavioral of barelsaupisomnula is component mux8u1 is Port ( CH0 : in STD_LOGIC; CH1 : in STD_LOGIC; CH2 : in STD_LOGIC; CH3 : in STD_LOGIC; CH4 : in STD_LOGIC; CH5 : in STD_LOGIC; CH6 : in STD_LOGIC; CH7 : in STD_LOGIC; S0 : in STD_LOGIC; S1 : in STD_LOGIC; S2 : in STD_LOGIC; Q : out STD_LOGIC); end component; begin MUX_7: MUX_6: MUX_5: MUX_4: MUX_3: MUX_2: MUX_1: MUX_0: mux8u1 mux8u1 mux8u1 mux8u1 mux8u1 mux8u1 mux8u1 mux8u1 port port port port port port port port map map map map map map map map (D(7),D(6),D(5),D(4),D(3),D(2),D(1),D(0),S(0),S(1),S(2),Q(7)); (D(6),D(5),D(4),D(3),D(2),D(1),D(0),'0' ,S(0),S(1),S(2),Q(6)); (D(5),D(4),D(3),D(2),D(1),D(0),'0' ,'0' ,S(0),S(1),S(2),Q(5)); (D(4),D(3),D(2),D(1),D(0),'0' ,'0' ,'0' ,S(0),S(1),S(2),Q(4)); (D(3),D(2),D(1),D(0),'0' ,'0' ,'0' ,'0' ,S(0),S(1),S(2),Q(3)); (D(2),D(1),D(0),'0' ,'0' ,'0' ,'0' ,'0' ,S(0),S(1),S(2),Q(2)); (D(1),D(0),'0' ,'0' ,'0' ,'0' ,'0' ,'0' ,S(0),S(1),S(2),Q(1)); (D(0),'0' ,'0' ,'0' ,'0' ,'0' ,'0' ,'0' ,S(0),S(1),S(2),Q(0));
end Behavioral;
Test kod:
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VHDL Tutorijali
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT barelsaupisomnula PORT( D : IN std_logic_vector(7 downto 0); S : IN std_logic_vector(2 downto 0); Q : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs SIGNAL D : SIGNAL S : --Outputs SIGNAL Q : BEGIN -- Instantiate the Unit Under Test (UUT) uut: barelsaupisomnula PORT MAP( D => D, S => S, Q => Q ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; D<="10010110"; S<="000"; wait for 50 ns; assert(Q="10010110") report "Greska 1" severity warning; S<="001"; wait for 20 ns; assert(Q="00101100") report "Greska 2" severity warning; S<="010"; wait for 50 ns; assert(Q="01011000") report "Greska 3" severity warning; S<="011"; wait for 50 ns; assert(Q="10110000") report "Greska 4" severity warning; S<="100"; wait for 50 ns; assert(Q="01100000") report "Greska 5" severity warning; S<="101"; wait for 50 ns; assert(Q="11000000") report "Greska 6" severity warning; S<="110"; wait for 50 ns; assert(Q="10000000") report "Greska 7" severity warning; std_logic_vector(7 downto 0) := (others=>'0'); std_logic_vector(2 downto 0) := (others=>'0'); std_logic_vector(7 downto 0);
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VHDL Tutorijali
S<="111"; wait for 50 ns; assert(Q="00000000") report "Greska 8" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
Zadatak 12: (1 bitni puni oduzima) Data je tabela istine 16. koja opisuje funkcionalnost 1 bitnog oduzimaa. Napisati VHDL kod koji opisuje funkcionalnost datog kola. Napisati nekoliko testnih sluajeva koja e pokazati da kolo radi ispravno.
Tabela 16. Tabela istine za jednobitni puni oduzima
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bitnioduzimac is Port ( Cin : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end bitnioduzimac; architecture Behavioral of bitnioduzimac is begin S<=(Cin and B)or(Cin and not A)or(not A and B); Cout <= (Cin and A and B) or (Cin and not A and not B) or(not Cin and A and not B) or(not Cin and not A and B); end Behavioral;
Test kod:
LIBRARY ieee;
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VHDL Tutorijali
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT bitnioduzimac PORT( Cin : IN std_logic; A : IN std_logic; B : IN std_logic; S : OUT std_logic; Cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL Cin : std_logic := '0'; SIGNAL A : std_logic := '0'; SIGNAL B : std_logic := '0'; --Outputs SIGNAL S : std_logic; SIGNAL Cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: bitnioduzimac PORT MAP( Cin => Cin, A => A, B => B, S => S, Cout => Cout ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; Cin<='0'; A<='0'; B<='0'; wait for 10 ns; assert(S='0' and Cout='0') report "Greska 1" severity warning; wait for 50 ns; Cin<='0'; A<='0'; B<='1'; wait for 10 ns; assert(S='1' and Cout='1') report "Greska 2" severity warning; wait for 50 ns; Cin<='0'; A<='1'; B<='0'; wait for 10 ns; assert(S='0' and Cout='1') report "Greska 3" severity warning; wait for 50 ns; Cin<='0';
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VHDL Tutorijali
A<='1'; B<='1'; wait for 10 ns; assert(S='0' and Cout='0') report "Greska 4" severity warning; wait for 50 ns; Cin<='1'; A<='0'; B<='0'; wait for 10 ns; assert(S='1' and Cout='1') report "Greska 5" severity warning; wait for 50 ns; Cin<='1'; A<='0'; B<='1'; wait for 10 ns; assert(S='1' and Cout='0') report "Greska 6" severity warning; wait for 50 ns; Cin<='1'; A<='1'; B<='0'; wait for 10 ns; assert(S='0' and Cout='0') report "Greska 7" severity warning; wait for 50 ns; Cin<='1'; A<='1'; B<='1'; wait for 10 ns; assert(S='1' and Cout='1') report "Greska 8" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 13: (BCDtoBCD Excess3) Napravite konvertor BCD koda u Excess 3 kod koritenjem 4 bitnog sabiraa. Treba voditi rauna da se brojevi u Excess 3 kodu dobiju dodavanjem broja 3 odgovarajuoj BCD cifri. Blok shema ovog kola je data na slici 8.
Slika 8. Blok shema BCDtoBCD Excess3
Source kod 1: (potpuni 1 bitni sumator)

library IEEE;
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VHDL Tutorijali
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity punisumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end punisumator; architecture Behavioral of punisumator is begin S<=Cin xor A xor B; Cout<=(Cin and A)or(Cin and B)or(A and B); end Behavioral;
Source kod 2: (etverobitni puni sabira)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cetverobitnisabirac is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC); end cetverobitnisabirac; architecture Behavioral of cetverobitnisabirac is component punisumator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end component; signal c0, c1,c2: STD_LOGIC; begin FA0: punisumator FA1: punisumator FA2: punisumator FA3: punisumator end Behavioral; port port port port map map map map (Cin, (c0, (c1, (c2, A(0), A(1), A(2), A(3), B(0), B(1), B(2), B(3), S(0), S(1), S(2), S(3), c0); c1); c2); Cout);
Source kod 3: (NBCD to Excess 3)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity NBCDtoE3 is Port ( nbcd : in STD_LOGIC_VECTOR (3 downto 0); excess3 : out STD_LOGIC_VECTOR (3 downto 0)); end NBCDtoE3;
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VHDL Tutorijali
architecture Behavioral of NBCDtoE3 is component cetverobitnisabirac is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC); end component; signal neidevani:std_logic; begin konvertor: cetverobitnisabirac port map(nbcd,"0011",'0',excess3,neidevani); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT NBCDtoE3 PORT( nbcd : IN std_logic_vector(3 downto 0); excess3 : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL nbcd : std_logic_vector(3 downto 0) := (others=>'0'); std_logic_vector(3 downto 0);
--Outputs SIGNAL excess3 : BEGIN
-- Instantiate the Unit Under Test (UUT) uut: NBCDtoE3 PORT MAP( nbcd => nbcd, excess3 => excess3 ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; nbcd<="0000"; wait for 50 ns; assert(excess3="0011") report "Greska 0" severity warning; nbcd<="0001"; wait for 50 ns; assert(excess3="0100") report "Greska 1" severity warning; nbcd<="0010"; wait for 50 ns; assert(excess3="0101") report "Greska 2" severity warning;
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VHDL Tutorijali
nbcd<="0011"; wait for 50 ns; assert(excess3="0110") report "Greska 3" severity warning; nbcd<="0100"; wait for 50 ns; assert(excess3="0111") report "Greska 4" severity warning; nbcd<="0101"; wait for 50 ns; assert(excess3="1000") report "Greska 5" severity warning; nbcd<="0110"; wait for 50 ns; assert(excess3="1001") report "Greska 6" severity warning; nbcd<="0111"; wait for 50 ns; assert(excess3="1010") report "Greska 7" severity warning; nbcd<="1000"; wait for 50 ns; assert(excess3="1011") report "Greska 8" severity warning; nbcd<="1001"; wait for 50 ns; assert(excess3="1100") report "Greska 9" severity warning; -- Place stimulus here wait; -- will wait forever END PROCESS; END;
3.
Tutorijal broj 3: Sekvencijalne komponente
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VHDL Tutorijali
Zadatak 1: Napraviti dizajn asinhronog RS ip - opa na bazi NILI kola realizovanog u VHDLu. Analizirati rad kola.
Slika 9. Asinhroni RS flip flop na bazi NILI kola
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asinhroniRSFFniliKola is Port ( R : in STD_LOGIC; S : in STD_LOGIC; Q : inout STD_LOGIC; Qneg : inout STD_LOGIC); end asinhroniRSFFniliKola; architecture Behavioral of asinhroniRSFFniliKola is begin process(R,S,Q,Qneg) begin Q<=R nor Qneg; Qneg<=S nor Q; end process; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT asinhroniRSFFniliKola PORT( R : IN std_logic; S : IN std_logic; Q : INOUT std_logic; Qneg : INOUT std_logic ); END COMPONENT;
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VHDL Tutorijali
--Inputs SIGNAL R : SIGNAL S : SIGNAL Q :
std_logic := '0'; std_logic := '0'; std_logic; std_logic;
--Outputs SIGNAL Qneg : BEGIN
-- Instantiate the Unit Under Test (UUT) uut: asinhroniRSFFniliKola PORT MAP( R => R, S => S, Q => Q, Qneg => Qneg ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 10 ns; R<='0'; S<='0'; wait for 20 ns; assert(Q='U' and Qneg='U') report "Greska 1" severity warning; R<='0'; S<='1'; wait for 20 ns; assert(Q='1' and Qneg='0') report "Greska 2" severity warning; R<='1'; S<='0'; wait for 20 ns; assert(Q='0' and Qneg='1') report "Greska 3" severity warning; R<='0'; S<='0'; wait for 20 ns; assert(Q='0' and Qneg='1') report "Greska 5" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 2:
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VHDL Tutorijali
Na osnovu zadatka 1. realizirati asinhroni RS ip - op pomou NI kola i provjeriti ispravnost rada kola.
Slika 10. Asinhroni RS flip flop na bazi NI kola
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AsinhroniRSFF_Nikola is Port ( Rneg : in STD_LOGIC; Sneg : in STD_LOGIC; Q : inout STD_LOGIC; Qneg : inout STD_LOGIC); end AsinhroniRSFF_Nikola; architecture Behavioral of AsinhroniRSFF_Nikola is begin process (Rneg, Sneg, Q, Qneg) begin Q<=Sneg nand Qneg; Qneg<=Rneg nand Q; end process; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AsinhroniRSFF_Nikola PORT( Rneg : IN std_logic; Sneg : IN std_logic; Q : INOUT std_logic; Qneg : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL Rneg : SIGNAL Sneg : std_logic := '0'; std_logic := '0';
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VHDL Tutorijali
--BiDirs SIGNAL Q : std_logic; SIGNAL Qneg : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: AsinhroniRSFF_Nikola PORT MAP( Rneg => Rneg, Sneg => Sneg, Q => Q, Qneg => Qneg ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 10 ns; Rneg<='0'; Sneg<='1'; wait for 20 ns; assert(Q='0' and Qneg='1') report "Greska 1" severity warning; Rneg<='1'; Sneg<='0'; wait for 20 ns; assert(Q='1' and Qneg='0') report "Greska 2" severity warning; Rneg<='1'; Sneg<='1'; wait for 20 ns; assert(Q='1' and Qneg='0') report "Greska 3" severity warning; Rneg<='0'; Sneg<='1'; wait for 20 ns; assert(Q='0' and Qneg='1') report "Greska 4" severity warning; Rneg<='1'; Sneg<='1'; wait for 20 ns; assert(Q='0' and Qneg='1') report "Greska 5" severity warning; END PROCESS; END;
Zadatak 3:
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VHDL Tutorijali
Napraviti dizajn asinhronog JK ip - opa napisanog u VHDLu. Napisati niz testnih sluajeva koji e ispitati ispravnost rada kola, te popuniti tabelu prelaza stanja JK ip -opa na osnovu simulacije kola.
Slika 11. Asinhroni JK flip flop Tabela 17. Tabela prelaza stanja JK flip - flopa
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Q : inout STD_LOGIC:='0'; Qneg : inout STD_LOGIC:='1'); end JKFF; architecture Behavioral of JKFF is begin process(J, K) begin if (J='0' and K ='0') then Q <= Q; elsif (J='0' and K='1') then Q <= '0'; elsif (J='1' and K='0') then Q <='1'; elsif (J='1' and K='1') then Q <= not Q; end if;
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VHDL Tutorijali
end process; Qneg <= not Q; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT JKFF PORT( J : IN std_logic; K : IN std_logic; Q : INOUT std_logic; Qneg : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL J : SIGNAL K : std_logic := '0'; std_logic := '0';
--BiDirs SIGNAL Q : std_logic; SIGNAL Qneg : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: JKFF PORT MAP( J => J, K => K, Q => Q, Qneg => Qneg ); tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here J<='0'; K<='0'; wait for 10 ns; assert (Q='0' and Qneg='1') report "Greska 1" severity warning; J<='1'; K<='0'; wait for 10 ns; assert (Q='1' and Qneg='0') report "Greska 2" severity warning; J<='0'; K<='1'; wait for 10 ns; assert (Q='0' and Qneg='1') report "Greska 3" severity warning; J<='1';
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VHDL Tutorijali
K<='1'; wait for 10 ns; assert (Q='1' and Qneg='0') report "Greska 4" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 4: Napraviti dizajn D lea napisan u VHDLu, kao i nekoliko testnih sluajeva za ovo kolo. Nakon to se realizira dato kolo, popuniti tabelu prelaza stanja D lea na osnovu simulacije kola.
Tabela 18. Tabela prelaza stanja D flip flopa
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DFF is Port ( D : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end DFF; architecture Behavioral of DFF is begin process (D, Clk) begin if Clk = '1' then Q <= D; Qneg <= not D; end if; end process; end Behavioral;
Test kod:
LIBRARY ieee;
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VHDL Tutorijali
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT DFF PORT( D : IN std_logic; Clk : IN std_logic; Q : OUT std_logic; Qneg : OUT std_logic ); END COMPONENT; --Inputs SIGNAL D : std_logic := '0'; SIGNAL Clk : std_logic := '0'; --Outputs SIGNAL Q : std_logic; SIGNAL Qneg : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: DFF PORT MAP( D => D, Clk => Clk, Q => Q, Qneg => Qneg ); -- Dodaje se kod koji simulira clock signal clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here D <= '1'; wait for 30 ns; assert(Q = '1' and Qneg D <= '0'; wait for 15 ns; assert(Q = '0' and Qneg D <= '1'; wait for 20 ns; assert(Q = '1' and Qneg D <= '1'; wait for 15 ns; assert(Q = '1' and Qneg D <= '0'; wait for 40 ns; assert(Q = '0' and Qneg D <= '1';
= '0') report("Greska 1") severity warning; = '1') report("Greska 2") severity warning; = '0') report("Greska 3") severity warning; = '0') report("Greska 4") severity warning; = '1') report("Greska 5") severity warning;
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VHDL Tutorijali
wait for 30 ns; assert(Q = '1' and Qneg = '0') report("Greska 6") severity warning; D <= '0'; wait for 50 ns; assert(Q = '0' and Qneg = '1') report("Greska 7") severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 5: Napraviti dizajn D flip flopa okidan sa uzlaznom ivicom sata sa signalima preset i clear napisan u VHDLu, kao i nekoliko testnih sluajeva za ovo kolo. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DFF is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Clr : in STD_LOGIC; Pre : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end DFF; architecture Behavioral of DFF is begin process(Clk) begin IF (Clk'event) and (Clk='1') then --za slucaj okidanja sa silaznom ivicom --prethodna linija koda se zapisuje kao: --IF (Clk'event) and (Clk='0') then if Clr = '1' then Q <= '0'; Qneg <= '1'; elsif Pre = '1' then Q <= '1'; Qneg <= '0'; else Q <= D; Qneg <= not D; end if; end if; end process; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL;
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VHDL Tutorijali
USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT DFF PORT( Clk : IN std_logic; D : IN std_logic; Clr : IN std_logic; Pre : IN std_logic; Q : OUT std_logic; Qneg : OUT std_logic ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL D : std_logic := '0'; SIGNAL Clr : std_logic := '0'; SIGNAL Pre : std_logic := '0'; --Outputs SIGNAL Q : std_logic; SIGNAL Qneg : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: DFF PORT MAP( Clk => Clk, D => D, Clr => Clr, Pre => Pre, Q => Q, Qneg => Qneg ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus D <= '1'; wait for 10 ns; assert (Q='1' and D <= '0'; wait for 20 ns; assert (Q='0' and D <= '1'; wait for 20 ns; assert (Q='1' and D <= '0'; wait for 20 ns; here Qneg='0') report "Greska 1" severity warning; Qneg='1') report "Greska 2" severity warning; Qneg='0') report "Greska 3" severity warning;
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VHDL Tutorijali
assert (Q='0' and D <= '1'; wait for 20 ns; assert (Q='1' and D <= '0'; wait for 20 ns; assert (Q='0' and D <= '1'; wait for 20 ns; assert (Q='1' and D <= '0'; wait for 20 ns; assert (Q='0' and Qneg='1') report "Greska 4" severity warning; Qneg='0') report "Greska 5" severity warning; Qneg='1') report "Greska 6" severity warning; Qneg='0') report "Greska 7" severity warning; Qneg='1') report "Greska 8" severity warning;
Zadatak 6: Dizajnirati T flip flop okidan uzlaznom ivicom sata sa signalima reset i clock enable. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TFF is Port ( Clk : in STD_LOGIC; Reset : in STD_LOGIC; Clk_enable : in STD_LOGIC; T : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end TFF; architecture Behavioral of TFF is signal temp: std_logic:='0'; begin process (Clk) begin if Clk'event and Clk='1' then if Reset='1' then temp <= '0'; elsif Clk_enable ='1' then if T='0' then temp <= temp; elsif T='1' then temp <= not (temp); end if; end if; end if; end process; Q<=temp; Qneg<=not temp; end Behavioral;
Test kod:
LIBRARY ieee;
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VHDL Tutorijali
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT TFF PORT( Clk : IN std_logic; Reset : IN std_logic; Clk_enable : IN std_logic; T : IN std_logic; Q : OUT std_logic; Qneg : OUT std_logic ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL Reset : std_logic := '0'; SIGNAL Clk_enable : std_logic := '1'; SIGNAL T : std_logic := '0'; --Outputs SIGNAL Q : std_logic; SIGNAL Qneg : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: TFF PORT MAP( Clk => Clk, Reset => Reset, Clk_enable => Clk_enable, T => T, Q => Q, Qneg => Qneg ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; T<= '1'; wait for 25 ns; assert (Q='0' and T<= '0'; wait for 20 ns; assert (Q='0' and T<= '1'; wait for 25 ns; assert (Q='1' and T<= '0'; wait for 15 ns; assert (Q='1' and
Qneg='1') report "Greska 1" severity warning; Qneg='1') report "Greska 2" severity warning; Qneg='0') report "Greska 3" severity warning; Qneg='0') report "Greska 4" severity warning;
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VHDL Tutorijali
T<= '1'; wait for 10 ns; assert (Q='0' and T<= '0'; wait for 15 ns; assert (Q='0' and T<= '1'; wait for 20 ns; assert (Q='1' and T<= '0'; wait for 15 ns; assert (Q='0' and
Qneg='1') report "Greska 5" severity warning; Qneg='1') report "Greska 6" severity warning; Qneg='0') report "Greska 7" severity warning; Qneg='1') report "Greska 8" severity warning;
Zadatak 7: Na osnovu dizajna D flip flopa okidanog uzlaznom ivicom sata potrebno je dizajnirati 8 bitni registar. Upis u registar je paralelno, kao i oitanje. Napisati nekoliko testnih sluajeva kojim ete provjeriti ispravnost rada kola. Source kod 1: (D flip flop)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DFF is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Clr : in STD_LOGIC; Pre : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end DFF; architecture Behavioral of DFF is begin process(Clk) begin IF (Clk'event) and (Clk='1') then if Clr = '1' then Q <= '0'; Qneg <= '1'; elsif Pre = '1' then Q <= '1'; Qneg <= '0'; else Q <= D; Qneg <= not D; end if; end if; end process; end Behavioral;
Source kod 2: (8 bitni registar na bazi DFF)

library IEEE; use IEEE.STD_LOGIC_1164.ALL;
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VHDL Tutorijali
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity registar is Port ( D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0); Qneg : out STD_LOGIC_VECTOR (7 downto 0); Clk : in STD_LOGIC; Clr : in std_logic; Pre : in std_logic); end registar; architecture Behavioral of registar is component DFF is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Clr : in STD_LOGIC; Pre : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end component; begin DFF_0: DFF DFF_1: DFF DFF_2: DFF DFF_3: DFF DFF_4: DFF DFF_5: DFF DFF_6: DFF DFF_7: DFF end Behavioral; PORT PORT PORT PORT PORT PORT PORT PORT MAP MAP MAP MAP MAP MAP MAP MAP (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), Clr, Clr, Clr, Clr, Clr, Clr, Clr, Clr, Pre, Pre, Pre, Pre, Pre, Pre, Pre, Pre, Q(0), Q(1), Q(2), Q(3), Q(4), Q(5), Q(6), Q(7), Qneg(0)); Qneg(1)); Qneg(2)); Qneg(3)); Qneg(4)); Qneg(5)); Qneg(6)); Qneg(7));
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS COMPONENT registar PORT( D : IN std_logic_vector(7 downto 0); Clk : IN std_logic; Clr : IN std_logic; Pre : IN std_logic; Q : OUT std_logic_vector(7 downto 0); Qneg : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL Clr : std_logic := '0'; SIGNAL Pre : std_logic := '0'; SIGNAL D : std_logic_vector(7 downto 0) := (others=>'0'); --Outputs SIGNAL Q : std_logic_vector(7 downto 0); SIGNAL Qneg : std_logic_vector(7 downto 0);
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VHDL Tutorijali
BEGIN -- Instantiate the Unit Under Test (UUT) uut: registar PORT MAP( D => D, Q => Q, Qneg => Qneg, Clk => Clk, Clr => Clr, Pre => Pre ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; Clr<='0'; Pre<='0'; wait for 50 ns; D<="01010101"; wait for 25 ns; assert (Q="01010101" and Qneg="10101010") report "Greska 1" severity warning; Clr<='1'; wait for 25 ns; assert (Q="00000000" and Qneg="11111111") report "Greska 2" severity warning; Clr<='0'; Pre<='1'; wait for 25 ns; assert (Q="11111111" and Qneg="00000000") report "Greska 3" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 8:
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VHDL Tutorijali
Na osnovu dizajn iz zadatka 7 dizajnirati 32 bitni registar. Potrebno je modifikovati dizajn kola tako da se ima signal OC (engl. Output Control) koji kada je aktivan stanje registar se prenosi na izlaz. Napisati niz testnih sluajeva kojim e se ispitati ispravnost rada kola. Source kod 1: (D flip flop)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DFF is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Clr : in STD_LOGIC; Pre : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC); end DFF; architecture Behavioral of DFF is begin process(Clk) begin IF (Clk'event) and (Clk='1') then if Clr = '1' then Q <= '0'; Qneg <= '1'; elsif Pre = '1' then Q <= '1'; Qneg <= '0'; else Q <= D; Qneg <= not D; end if; end if; end process; end Behavioral;
Source kod 2: (8 bitni registar na bazi DFF)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity registar is Port ( D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0); Qneg : out STD_LOGIC_VECTOR (7 downto 0); Clk : in STD_LOGIC; Clr : in std_logic; Pre : in std_logic); end registar; architecture Behavioral of registar is component DFF is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Clr : in STD_LOGIC; Pre : in STD_LOGIC; Q : out STD_LOGIC; Qneg : out STD_LOGIC);
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VHDL Tutorijali
end component; begin DFF_0: DFF DFF_1: DFF DFF_2: DFF DFF_3: DFF DFF_4: DFF DFF_5: DFF DFF_6: DFF DFF_7: DFF end Behavioral; PORT PORT PORT PORT PORT PORT PORT PORT MAP MAP MAP MAP MAP MAP MAP MAP (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, (CLk, D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), Clr, Clr, Clr, Clr, Clr, Clr, Clr, Clr, Pre, Pre, Pre, Pre, Pre, Pre, Pre, Pre, Q(0), Q(1), Q(2), Q(3), Q(4), Q(5), Q(6), Q(7), Qneg(0)); Qneg(1)); Qneg(2)); Qneg(3)); Qneg(4)); Qneg(5)); Qneg(6)); Qneg(7));
Source kod 3: (32 bitni registar)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity registar32b is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC_VECTOR (31 downto 0); Clr : in STD_LOGIC; Pre : in STD_LOGIC; OE : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (31 downto 0); Qneg : out STD_LOGIC_VECTOR (31 downto 0)); end registar32b; architecture Behavioral of registar32b is component registar is Port ( D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0); Qneg : out STD_LOGIC_VECTOR (7 downto 0); Clk : in STD_LOGIC; Clr : in std_logic; Pre : in std_logic); end component; signal temp,tempn: std_logic_vector (31 downto 0); begin Bajt3: registar PORT MAP (D(31 downto 24),temp(31 downto 24),tempn(31 downto 24), Clk, Clr, Pre); Bajt2: registar PORT MAP (D(23 downto 16),temp(23 downto 16),tempn(23 downto 16), Clk, Clr, Pre); Bajt1: registar PORT MAP (D(15 downto 8), temp(15 downto 8), tempn(15 downto 8), Clk, Clr, Pre); Bajt0: registar PORT MAP (D(7 downto 0), Clk, Clr, Pre); Q<=temp when OE='1'; Qneg<=tempn when OE='1'; end Behavioral; temp(7 downto 0), tempn(7 downto 0),
Test kod:
LIBRARY ieee;
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VHDL Tutorijali
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT registar32b PORT( Clk : IN std_logic; D : IN std_logic_vector(31 downto 0); Clr : IN std_logic; Pre : IN std_logic; OE : IN std_logic; Q : OUT std_logic_vector(31 downto 0); Qneg : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL Clr : std_logic := '0'; SIGNAL Pre : std_logic := '0'; SIGNAL OE : std_logic := '0'; SIGNAL D : std_logic_vector(31 downto 0) := (others=>'0'); --Outputs SIGNAL Q : std_logic_vector(31 downto 0); SIGNAL Qneg : std_logic_vector(31 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: registar32b PORT MAP( Clk => Clk, D => D, Clr => Clr, Pre => Pre, OE => OE, Q => Q, Qneg => Qneg ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; D<="10101010101010101010101010101010"; wait for 10 ns; OE<='1'; wait for 40 ns; assert(Q="10101010101010101010101010101010") report "Greska 1" severity warning; OE<='0'; D<="00000000000000000000001111111111";
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wait for 40 ns; assert (Q="10101010101010101010101010101010") report "Greska 2" severity warning; OE<='1'; wait for 55 ns; assert (Q="00000000000000000000001111111111") report "Greska 3" severity warning; clr<='1'; wait for 35 ns; assert (Q="00000000000000000000000000000000") report "Greska 4" severity warning; clr<='0'; pre<='1'; wait for 35 ns; assert (Q="11111111111111111111111111111111") report "Greska 5" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 9: Na slici 12 je data struktura 4 bitnog ift registra realizovanog koritenjem JK flip flopova. Dizajnirati sinhroni JK flip flop okidan silaznom ivicom sata. Realizirati kolo dato na slici pomou formiranog dizajna JK flip flopa. Provjeriti ispravnost rada kola pomou nekoliko testnih sluajeva.
Slika 12. ift registar na bazi JK flip flopa
Source kod 1: (JK flip flop)

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY JKFF IS PORT ( J : IN STD_LOGIC; K : IN STD_LOGIC; Clk : IN STD_LOGIC; Q : INOUT STD_LOGIC; Qneg : INOUT STD_LOGIC); END JKFF; ARCHITECTURE arch_JKFF OF JKFF IS BEGIN PROCESS(Clk) VARIABLE temp: STD_LOGIC; BEGIN temp := Q; IF (CLK'EVENT) AND (CLK='0') THEN IF (J = '0' AND K = '0') THEN Q <= temp;
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Qneg <= NOT temp; ELSIF (J = '0' AND K = '1') THEN Q <= '0'; Qneg <= '1'; ELSIF (J = '1' AND K = '0') THEN Q <= '1'; Qneg <= '0'; ELSIF (J = '1' AND K = '1') THEN Q <= NOT temp; Qneg <= temp; END IF; END IF; END PROCESS; END arch_JKFF;
Source kod 2: (4 bitni shift registar)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shift4bita is Port ( ulaz : in STD_LOGIC; Clk : in STD_LOGIC; izlaz : inout STD_LOGIC; nizlaz : inout STD_LOGIC); end shift4bita; architecture Behavioral of shift4bita is component JKFF IS PORT ( J : IN STD_LOGIC; K : IN STD_LOGIC; Clk : IN STD_LOGIC; Q : INOUT STD_LOGIC; Qneg : INOUT STD_LOGIC); end component; signal c0, c1, c2, c3, c4, c5, x: STD_LOGIC; begin x <= NOT ulaz; JKFF_0: JKFF PORT MAP (ulaz, x, Clk, c0, c1); JKFF_1: JKFF PORT MAP (c0, c1, Clk, c2, c3); JKFF_2: JKFF PORT MAP (c2, c3, Clk, c4, c5); JKFF_3: JKFF PORT MAP (c4, c5, Clk, izlaz, nizlaz); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT shift4bita PORT( ulaz : IN std_logic; Clk : IN std_logic; izlaz : INOUT std_logic; nizlaz : INOUT std_logic
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); END COMPONENT; --Inputs SIGNAL ulaz : std_logic := '0'; SIGNAL Clk : std_logic := '0'; --BiDirs SIGNAL izlaz : std_logic; SIGNAL nizlaz : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: shift4bita PORT MAP( ulaz => ulaz, Clk => Clk, izlaz => izlaz, nizlaz => nizlaz ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; --period kloka iznosi 20 ns, --petrobno su cetiri perioda da se upisu 4 bita wait for 5 ns; ulaz<='1'; wait for 20 ns; ulaz<='0'; wait for 20 ns; ulaz<='1'; wait for 20 ns; ulaz<='1'; -- Ako se prvo upisivao 0 bit, podatak je oblika 1101: wait for 25 ns; assert (izlaz='1') report "Greska 1" severity warning; wait for 20 ns; assert (izlaz='0') report "Greska 2" severity warning; wait for 20 ns; assert (izlaz='1') report "Greska 3" severity warning; wait for 20 ns; assert (izlaz='1') report "Greska 4" severity warning; wait; -- will wait forever END PROCESS; END;
Zadatak 10:
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U VHDLu dizajnirati 3 bitni asinhroni/serijski broja na bazi JK flip flopova. U tabeli 19 je data promjena izlaza Qi u odnosu na vrijeme t mjereno taktom sata koji se dovodi na prvi flip flop, kao i realizacija datog kola koristei JK flip flopove. Ovaj broja se jo naziva broja po modulu 8.
Tabela 19. Tabela prelaza stanja asinhronog 3-bitnog brojaa.
Slika 13. Realizacija 3 bitnog asinhronog brojaa

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY JKFF IS PORT ( J : IN STD_LOGIC; K : IN STD_LOGIC; Clk : IN STD_LOGIC; Q : INOUT STD_LOGIC:='0'; Qneg : INOUT STD_LOGIC:='1'); END JKFF; ARCHITECTURE arch_JKFF OF JKFF IS BEGIN PROCESS(Clk) VARIABLE temp: STD_LOGIC; BEGIN temp := Q; IF (CLK'EVENT) AND (CLK='1') THEN IF (J = '0' AND K = '0') THEN Q <= temp; Qneg <= NOT temp; ELSIF (J = '0' AND K = '1') THEN Q <= '0'; Qneg <= '1'; ELSIF (J = '1' AND K = '0') THEN Q <= '1'; Qneg <= '0'; ELSIF (J = '1' AND K = '1') THEN
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Q <= NOT temp; Qneg <= temp; END IF; END IF; END PROCESS; END arch_JKFF;
Source kod 2: (3 bitni brojac)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac3bita is Port ( Clk : in STD_LOGIC; High : in STD_LOGIC; Q0 : inout STD_LOGIC; Q1 : inout STD_LOGIC; Q2 : inout STD_LOGIC; Q2neg : inout std_logic); end brojac3bita; architecture Behavioral of brojac3bita is component JKFF IS PORT ( J : IN STD_LOGIC; K : IN STD_LOGIC; Clk : IN STD_LOGIC; Q : INOUT STD_LOGIC; Qneg : INOUT STD_LOGIC); END component; signal qn1, qn2 : std_logic:='0'; begin JKFF1: JKFF port map (High, High, Clk, Q0, qn1); JKFF2: JKFF port map (High, High, qn1, Q1, qn2); JKFF3: JKFF port map (High, High, qn2, Q2, Q2neg); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac3bita PORT( Clk : IN std_logic; High : IN std_logic; Q0 : INOUT std_logic; Q1 : INOUT std_logic; Q2 : INOUT std_logic; Q2neg : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL High : std_logic := '0';
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--BiDirs SIGNAL Q0 : SIGNAL Q1 : SIGNAL Q2 : SIGNAL Q2neg BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac3bita PORT MAP( Clk => Clk, High => High, Q0 => Q0, Q1 => Q1, Q2 => Q2, Q2neg => Q2neg ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; High<='1'; wait for 160 ns; High<='0'; wait; -- will wait forever END PROCESS; END;
std_logic; std_logic; std_logic; : std_logic;
Zadatak 11:
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Dizajnirati serijski binarni broja koji broji u opsegu od 0 do 9, pri emu je prvo zabranjeno stanje broj 10. Koristiti JK flip flopove sa okidanjem na silaznoj ivici sata. Iz opsega brojanja se moe vidjeti da broja poinje sekvencu sa brojem nula, a zavrava sekvencu sa brojem 9, to znai da se radi o brojau po modulu 10. Ovaj broja se jo naziva dekadni serijski (asinhroni) broja. Za realizaciju ovog brojaa potrebna su etiri flip flopa, meutim koristit e se 10 stanja, a est e biti zabranjeno. Kada broja dosegne prvo zabranjeno stanja 10 (1010), sve flip flopove je potrebno resetovati, to e onemoguiti dolazak u ostala zabranjena stanja. Realizacija kola data je na slici 14.
Slika 14. Realizacija asinhronog/serijskog brojaa po modulu 10 koristenjem JK flip-flopova.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC:='0'; Qneg : inout STD_LOGIC:='1'); end JKFF; architecture Behavioral of JKFF is begin process (Clk,Res,Set) variable temp: STD_LOGIC; begin temp := Q; if Res='0' then Q <= '0'; Qneg <= '1'; elsif Set='1' then Q <= '1'; Qneg <= '0'; elsif Clk'event and Clk='0' then if (J='0' and K = '0') then Q <= temp; Qneg <= not temp;
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elsif (J='0' and K = '1') then Q <= '0'; Qneg <= '1'; elsif (J='1' and K='0') then Q <= '1'; Qneg <= '0'; elsif (J = '1' and K = '1') then Q <= not temp; Qneg <= temp; end if; end if; end process; end Behavioral;
Source kod 2: (broja)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac0do9 is Port ( High : in STD_LOGIC; Clk : in STD_LOGIC; Q0 : inout STD_LOGIC; Q1 : inout STD_LOGIC; Q2 : inout STD_LOGIC; Q3 : inout STD_LOGIC); end brojac0do9; architecture Behavioral of brojac0do9 is component JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC; Qneg : inout STD_LOGIC); end component; signal qn0,qn1,qn2,qn3:std_logic; signal Res:std_logic:='1'; signal Set:std_logic:='0'; begin JKFF0: JKFF port map (High, High, JKFF1: JKFF port map (High, High, JKFF2: JKFF port map (High, High, JKFF3: JKFF port map (High, High, Res<=not (Q3 and Q1); end Behavioral;
Clk, Q0, Q1, Q2,
Res, Res, Res, Res,
Set,Q0,qn0); Set,Q1,qn1); Set,Q2,qn2); Set,Q3,qn3);
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac0do9 PORT(
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Clk : IN std_logic; High : IN std_logic; Q0 : INOUT std_logic; Q1 : INOUT std_logic; Q2 : INOUT std_logic; Q3 : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL High : std_logic := '0'; --BiDirs SIGNAL Q0 SIGNAL Q1 SIGNAL Q2 SIGNAL Q3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac0do9 PORT MAP( Clk => Clk, High => High, Q0 => Q0, Q1 => Q1, Q2 => Q2, Q3 => Q3 ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; High<='1'; -- Place stimulus here wait; -- will wait forever END PROCESS; END; : : : : std_logic; std_logic; std_logic; std_logic;
Zadatak 12:
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Realizirati asinhroni broja koji broji u opsegu od 2 do 12, pri emu je prvo zabranjeno stanje broj 13. Prilikom realizacije kola koristiti JK flip flopove sa okidanjem na silaznoj ivici sata, sa set i reset signalima. Source kod 1: (JK flip flop)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC:='0'; Qneg : inout STD_LOGIC:='1'); end JKFF; architecture Behavioral of JKFF is begin process (Clk,Res,Set) variable temp: STD_LOGIC; begin temp := Q; if Res='0' then Q <= '0'; Qneg <= '1'; elsif Set='1' then Q <= '1'; Qneg <= '0'; elsif Clk'event and Clk='0' then if (J='0' and K = '0') then Q <= temp; Qneg <= not temp; elsif (J='0' and K = '1') then Q <= '0'; Qneg <= '1'; elsif (J='1' and K='0') then Q <= '1'; Qneg <= '0'; elsif (J = '1' and K = '1') then Q <= not temp; Qneg <= temp; end if; end if; end process; end Behavioral;
Source kod 2: (broja od 2 do 12)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac2do12 is Port ( High : in STD_LOGIC; Clk : in STD_LOGIC; Q0 : inout STD_LOGIC; Q1 : inout STD_LOGIC; Q2 : inout STD_LOGIC;
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Q3 : inout end brojac2do12; STD_LOGIC);
architecture Behavioral of brojac2do12 is component JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC; Qneg : inout STD_LOGIC); end component; signal qn0,qn1,qn2,qn3:std_logic; signal Res:std_logic:='1'; signal Set:std_logic:='0'; begin JKFF0: JKFF port map (High, High, Clk, JKFF1: JKFF port map (High, High, Q0, JKFF2: JKFF port map (High, High, Q1, JKFF3: JKFF port map (High, High, Q2, Res<=not (Q3 and Q2 and Q0); end Behavioral;
Res, '1', Res, Res,
Set,Q0,qn0); not Res,Q1,qn1); Set,Q2,qn2); Set,Q3,qn3);
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac2do12 PORT( High : IN std_logic; Clk : IN std_logic; Q0 : INOUT std_logic; Q1 : INOUT std_logic; Q2 : INOUT std_logic; Q3 : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL High : std_logic := '0'; SIGNAL Clk : std_logic := '0'; --BiDirs SIGNAL Q0 SIGNAL Q1 SIGNAL Q2 SIGNAL Q3 BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac2do12 PORT MAP( High => High, Clk => Clk, Q0 => Q0, Q1 => Q1, Q2 => Q2, : : : : std_logic; std_logic; std_logic; std_logic;
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Q3 => Q3 ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; High<='1'; wait; -- will wait forever END PROCESS; END;
Zadatak 13: Dizajnirati broja koji generie sekvencu brojeva 0, 1, 2, 3, nakon ega poinje brojanje ispoetka (3 -> 0). Koristiti JK flip flopove prilikom realizacije. Traeni broja ima dva bita stanja (4 stanja = 2 2), iz ega se moe zakljuiti da su potrebna dva flip flopa da se realizuje kolo. Tabela prelaza i pobuda se potom moe definisati na sljedei nain:
Tabela 20. Tabela prelaza stanja 2-bitnog brojaa realizovanog JK flip-flopovima.
Tabela prelaza stanja se formira pomou tabele pobuda JK flip flopa, koja je navedena ispod.
Tabela 21. Tabela pobuda JK flip-flopa.
Iz tabele prelaza se potom dobiju optimalne funkcije za J0, K0, J1 i K1, koje glase:
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Dobijene su sve potrebne informacije za realizaciju ovog kola, pa se shodno tome moe nacrtati shema koja opisuje rad ovog kola.
Slika 15. Realizacija sinhronog/paralelnog brojaa koji broji od 0 do 3 koritenjem JK flip - flopova.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC:='0'; Qneg : inout STD_LOGIC:='1'); end JKFF; architecture Behavioral of JKFF is begin process (Clk,Res,Set) variable temp: STD_LOGIC; begin temp := Q; if Res='0' then Q <= '0'; Qneg <= '1'; elsif Set='1' then Q <= '1'; Qneg <= '0'; elsif Clk'event and Clk='0' then if (J='0' and K = '0') then Q <= temp; Qneg <= not temp; elsif (J='0' and K = '1') then Q <= '0'; Qneg <= '1'; elsif (J='1' and K='0') then Q <= '1';
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Qneg <= '0'; elsif (J = '1' and K = '1') then Q <= not temp; Qneg <= temp; end if; end if; end process; end Behavioral;
Source kod 2: (broja od 2 do 12)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac is Port ( High : in STD_LOGIC; Clk : in STD_LOGIC; Q0 : inout STD_LOGIC; Q1 : inout STD_LOGIC); end brojac; architecture Behavioral of brojac is component JKFF is Port ( J : in STD_LOGIC; K : in STD_LOGIC; Clk : in STD_LOGIC; Res : in STD_LOGIC; Set : in STD_LOGIC; Q : inout STD_LOGIC:='0'; Qneg : inout STD_LOGIC:='1'); end component; signal qn0,qn1,qn2,qn3:std_logic; signal Res:std_logic:='1'; signal Set:std_logic:='0'; begin JKFF0: JKFF port map (High, High, Clk, Res, Set,Q0,qn0); JKFF1: JKFF port map (Q0, Q0, Clk, Res, Set,Q1,qn1); end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac PORT( High : IN std_logic; Clk : IN std_logic; Q0 : INOUT std_logic; Q1 : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL High : std_logic := '0'; SIGNAL Clk : std_logic := '0';
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--BiDirs SIGNAL Q0 : SIGNAL Q1 : BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac PORT MAP( High => High, Clk => Clk, Q0 => Q0, Q1 => Q1 ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; High<='1'; wait; -- will wait forever END PROCESS; END;
std_logic; std_logic;
Zadatak 14: Realizirati 4 bitni sinhroni broja u VHDLu. Potrebno je napisati nekoliko testnih sluajeva kojim e se provjeriti ispravnost rada kola. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac is PORT ( Clk : IN STD_LOGIC; Q : out std_logic_vector(3 downto 0) ); end brojac; architecture Behavioral of brojac is begin PROCESS(Clk) VARIABLE TEMP: std_logic_vector(3 downto 0):="0000"; BEGIN IF(Clk'EVENT AND Clk='0') THEN IF (TEMP = "1111") THEN TEMP := "0000"; ELSE TEMP := TEMP + 1;
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END IF; Q <= TEMP; END IF; END PROCESS; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac PORT( Clk : IN std_logic; Q : out std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL Clk : --Outputs SIGNAL Q : BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac PORT MAP( Clk => Clk, Q => Q ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; -- Place stimulus here wait; -- will wait forever END PROCESS; END; std_logic := '0'; std_logic_vector(3 downto 0);
Zadatak 15: 93
VHDL Tutorijali
Dizajnirati dekadni sinhroni broja u VHDLu sa sedmosegmentnim prikazom broja i asinhronim resetom. Koristiti dizajn iz prethodnog zadatka sa modifikacijom koja e omoguiti brojanje ispoetka kada se doe do broja 10. Kao to se ve zna, sedmosegmentni prikaz broja moe dati prikaz brojeva od 0 do 9, tako da ne bi bilo ni mogue prikazati brojeve od 10 do 15 u decimalnoj notaciji, ali bi moglo u heksadecimalnoj.
Slika 16. Sedmosegmentni prikaz
Sedmosegmentni prikaz broja se realizuje pomou sedam integrisanih svjetleih (LED) dioda, koje se aktiviraju/deaktiviraju posebnim kontrolnim signalima. Kao to se vidi iz tabele 22 brojevi od 0 9 se predstavljaju u NBCD kodu i svaka kombinacija aktivira razliit skup dioda oznaenih sa a, b, c, d, e, f i g. Na slici 16. su predstavljene pozicije svih dioda na sedmosegmentom prikazu.
Tabela 22. Odgovarajue pobude dioda u odnosu na broj koji prikazuju.
Dec 0 1 2 3 4 5 6 7 8 9
X 0 0 0 0 0 0 0 0 1 1
Y 0 0 0 0 1 1 1 1 0 0
Z 0 0 1 1 0 0 1 1 0 0
W 0 1 0 1 0 1 0 1 0 1
a 1 0 1 1 0 1 1 1 1 1
b 1 1 1 1 0 0 0 1 1 1
c 1 1 0 1 1 1 1 1 1 1
d 1 0 1 1 0 1 1 0 1 1
e 1 0 1 0 0 0 1 0 1 0
f 1 0 0 0 1 1 1 0 1 1
g 0 0 1 1 1 1 1 0 1 1
VHDL kod koji opisuje rad projektovanog sedmosegmentnim prikazom broja:
dekadnog
sinhronog
brojaa
sa
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VHDL Tutorijali
Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; pause : in STD_LOGIC; count_out : out STD_LOGIC_VECTOR (6 downto 0)); end brojac; architecture Behavioral of brojac is begin process (clk, reset,pause) variable TEMP: INTEGER RANGE 0 to 10; begin if (reset = '1') then TEMP := 0; elsif (pause = '1') then -- ne radi nista elsif(clk'event and clk='0') then if (TEMP = 10) then TEMP := 0; else TEMP := TEMP + 1; end if; end IF; case temp is when 0 => count_out <= "1111110"; when 1 => count_out <= "0110000"; when 2 => count_out <= "1101101"; when 3 => count_out <= "1111001"; when 4 => count_out <= "0010011"; when 5 => count_out <= "1011011"; when 6 => count_out <= "1011111"; when 7 => count_out <= "1110000"; when 8 => count_out <= "1111111"; when 9 => count_out <= "1111011"; when others => null; end case; end process; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac PORT( clk : IN std_logic; reset : IN std_logic; pause : IN std_logic; count_out : OUT std_logic_vector(6 downto 0)
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VHDL Tutorijali
); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL reset : std_logic := '0'; SIGNAL pause : std_logic := '0'; --Outputs SIGNAL count_out : BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac PORT MAP( clk => clk, reset => reset, pause => pause, count_out => count_out ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; pause<='1'; wait for 100 ns; pause<='0'; -- Place stimulus here wait; -- will wait forever END PROCESS; END; std_logic_vector(6 downto 0);
Zadatak 16:
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VHDL Tutorijali
Realizirati 3 bitni broja unaprijed i unazad formalnim projektovanjem kola. Neka je sa S oznaen signal koji diktira ponaanje signala, tj. da li broji unaprijed ili unazad. Moe se ustanoviti da postoji 8 stanja (23) koji na osnovu signala S mijenjaju svoj poloaj. Source kod:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity brojac is port( Clk, S, reset : in std_logic; Q : out std_logic_vector(3 downto 0) ); end brojac; architecture Behavioral of brojac is signal temp: std_logic_vector(3 downto 0); begin process (Clk) begin if (reset = '1') then temp <= "0000"; elsif (Clk'event and Clk='1') then if (S='0') then if (temp = "0111") then temp <= "0000"; else temp <= temp + 1; end if; else if (temp = "0000") then temp <= "0111"; else temp <= temp - 1; end if; end if; end if; end process; Q <= temp; end Behavioral;
Test kod:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT brojac PORT( Clk : IN std_logic; S : IN std_logic; reset : IN std_logic; Q : OUT std_logic_vector(3 downto 0)
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VHDL Tutorijali
); END COMPONENT; --Inputs SIGNAL Clk : std_logic := '0'; SIGNAL S : std_logic := '0'; SIGNAL reset : std_logic := '0'; --Outputs SIGNAL Q : BEGIN -- Instantiate the Unit Under Test (UUT) uut: brojac PORT MAP( Clk => Clk, S => S, reset => reset, Q => Q ); clk_proc: process begin Clk <= '1'; wait for 10 ns; Clk <= '0'; wait for 10 ns; end process; tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; reset<='1'; wait for 5 ns; reset<='0'; wait for 50 ns; S<='1'; wait for 50 ns; S<='0'; wait; -- will wait forever END PROCESS; END; std_logic_vector(3 downto 0);
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UNIVERZITET U SARAJEVU ELEKTROTEHNIKI FAKULTET SARAJEVO MoE (Masters) studij, II godina Projektovanje sistema na ipu

Faris Hodi Automatika i elektronika Sarajevo, 2010. godine

Tutorijal broj 1: Osnovna kombinatorna kola u VHDLu

Napisati VHDL kod koji opisuje jednostavno logiko kolo sa slike 1.

Slika 1. Jednostavno logiko kolo

Na osnovu tabele istine moe se zapisati:

Slika 2. Shema jednostavnog kola Tabela 2. Tabela istine za kolo sa slike 2

Na osnovu tabele istine se moe zapisati:

y = abcd + abcd + abcd + abc d = ac d + abd

--Outputs SIGNAL y : BEGIN

Slika 3. Blok shema 4-u-1 multipleksera.

Tabela 5. Tabela istine za 4-u-1 multiplekser.

Source kod 1: (1 bitni 2 u 1 mux)

Source kod 2: (etverobitni 2 u 1 mux)

Slika 4. Dijagram kola Tabela 6. Tabela istine za kolo sa slike 4

Y 101 010 001 001 101 010 101 010

Source kod 1: (trobitni 2 u 1 mux)

Source kod 2: (kolo sa slike 4)

Tutorijal broj 2: Kombinacione komponente

Source kod (varijanta 1):

Test kod (varijanta 1):

Source kod (varijanta 2):

Test kod (varijanta 2):

wait; -- will wait forever END PROCESS; END;

Source kod 2 (varijanta 1):

Test kod (varijanta 1):

Source kod (varijanta 2):

Test kod (varijanta 2):

Tabela 10. Potpuna tabela istine za 4-u-2 prioretni koder

Slika 7. Blok shema etverobitnog punog sabiraa

Source kod 1: (puni sabira)

Source kod 2: (etverobitni puni sabira)

Tabela 13. Tabela istine barel iftera sa rotiranjem u lijevo.

Source kod 1: (8 u 1 mux)

Source kod 2: (Barel ifter sa gubljenjem podataka)

Slika 8. Blok shema BCDtoBCD Excess3

Source kod 1: (potpuni 1 bitni sumator)

Source kod 2: (etverobitni puni sabira)

Source kod 3: (NBCD to Excess 3)

--Outputs SIGNAL excess3 : BEGIN

Tutorijal broj 3: Sekvencijalne komponente

Slika 9. Asinhroni RS flip flop na bazi NILI kola

std_logic := '0'; std_logic := '0'; std_logic; std_logic;

--Outputs SIGNAL Qneg : BEGIN

Slika 10. Asinhroni RS flip flop na bazi NI kola

wait; -- will wait forever END PROCESS; END;

wait; -- will wait forever END PROCESS; END;

Source kod 2: (8 bitni registar na bazi DFF)

Source kod 2: (8 bitni registar na bazi DFF)

Source kod 3: (32 bitni registar)

Slika 12. ift registar na bazi JK flip flopa

Source kod 1: (JK flip flop)

Source kod 2: (4 bitni shift registar)

Slika 13. Realizacija 3 bitnog asinhronog brojaa

Source kod 1: (JK flip flop)

Source kod 2: (3 bitni brojac)

std_logic; std_logic; std_logic; : std_logic;