EEET0486

2
VHDL

1. VHDL
2. VHDL Schematic
3. (symbol) VHDL Schematic
4. vector file

VHDL
Max+PlusII
1) Schematic ( gdf [Graphic Design File])
2) AHDL ( tdf [Text Design File])
3) VHDL ( vhd)
4) Verilog ( v)
Max+PlusII Student Edition Verilog
VHDL (VHSIC Hardware Description Language)
(Schematic) VHDL
(Modeling) (Model Simulation)
(Syntax) 2.1

2.1 VHDL
Vector file (*.vec)
Vector file Text file Vector file

2-1

EEET0486

. Waveform Editor (*.scf)

Waveform Editor vector file 1
Text Editor file.vec
VHDL

Library...
Use...
------------------Entity
------------------------------------Architecture
----------Begin
----------------------------------End

1. Library Package
Library Package Package
VHDL Library Library
Package Entity
2. Entity
entity VHDL
(Model)
3. Architecture
(Model) (Simulation)
(Port and
Generics) entity Architecture
End

2-2

EEET0486

2.1 0 F () VHDL
1. Max+PlusII

2. Text Editor count15.vhd D:\max2work\lab2

--Modern Digital System Design (FPGA LAB2)
--Electronics Engineering Dept.,MUT
________________

count15 __

_____ (
clk
up_down
qm

: __
: IN
: OUT

BIT;
___;
INTEGER RANGE 0 TO 9

___
END _________
_____________ ___ OF ________ IS
________
PROCESS (clk)
VARIABLE
cnt
VARIABLE
direction
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := ___;
END IF;

: INTEGER RANGE 0 TO 9;
: INTEGER;

IF (clk'EVENT AND clk = '1') THEN

cnt := cnt + _________ ;
END IF;
qm
<=
END PROCESS;

cnt;

END a;

3.
Assign | Device FLEX10K
EPF10k10LC84 - 3

2.2

2-3

EEET0486

4. (Compiler)
MAX+Plus|Compile Processing
Timing SNF Extractor

5. end time = 2.0us grid size = 25 ns

2.3
6. count15.VHD Text Editor
File | Create Default Symbol OK
7. Schematic File | New

Graphical Data File .gdf Graphic

Editor Symbol count15
counter15.gdf

2-4

EEET0486

2.2 7-Segment VHDL

1. Text Editor dec_7seg.VHD D:\TEMP\max2work\lab2
--Modern Digital System Design (FPGA LAB2)
--Electronics Engineering Dept.,MUT

____________________;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
________ dec_7seg IS
PORT (hex_digit
: ___
STD_LOGIC_VECTOR(3 DOWNTO 0);
segment_a, segment_b, segment_c,
segment_d, segment_e,
segment_f, segment_g
: ___ std_logic);
_______________
_______________ a OF dec_7seg IS
SIGNAL segment_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
______
PROCESS (Hex_digit)
BEGIN
CASE Hex_digit IS
WHEN "0000" =>
segment_data <= "1111110";
WHEN "0001" =>
segment_data <= "0110000";
WHEN "0010" =>
segment_data <= "1101101";
WHEN "0011" =>
segment_data <= "1111001";
WHEN "0100" =>
segment_data <= "0110011";
WHEN "0101" =>
segment_data <= "1011011";
WHEN "0110" =>
segment_data <= "1011111";
WHEN "0111" =>
segment_data <= "1110000";
WHEN "1000" =>
segment_data <= "1111111";
WHEN "1001" =>
segment_data <= "1111011";
WHEN "1010" =>
segment_data <= "1110111";
WHEN "1011" =>
segment_data <= "0011111";
WHEN "1100" =>
segment_data <= "1001110";
WHEN "1101" =>
segment_data <= "0111101";
WHEN "1110" =>
segment_data <= "1001111";
WHEN "1111" =>
segment_data <= "1000111";
WHEN OTHERS =>
segment_data <= "0111110";
END CASE;
END PROCESS;
-- extract segment data bits and invert
-- LED driver circuit is inverted
segment_a <=
NOT segment_data(6);
segment_b <= NOT segment_data(5);
segment_c <=
NOT segment_data(4);
segment_d <= NOT segment_data(3);
segment_e <=
NOT segment_data(2);
segment_f <=
NOT segment_data(1);
segment_g <= NOT segment_data(0);
_______

2-5

EEET0486

2. 3 6 2.1 2.4

2.4
3. Schematic counter15.gdf Symbol dec_7seg.gdf Symbol
dec_7seg .gdf

2.3 VHDL
1. Text Editor clock_div.VHD D:\TEMP\max2work\lab2
--Modern Digital System Design (FPGA LAB2)
--VHDL BY PRAYOON JAUNGJAN
--Electronics Engineering Dept.,MUT
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clock_div IS
PORT (
clock_12Mhz
: IN
STD_LOGIC;
clock_1MHz
: OUT
STD_LOGIC;
clock_50KHz
: OUT
STD_LOGIC;
clock_1KHz
: OUT
STD_LOGIC;
clock_50Hz
: OUT
STD_LOGIC;
clock_1Hz
: OUT
STD_LOGIC
);
END clock_div;
ARCHITECTURE arch_clock_div OF clock_div IS
SIGNAL count_1Mhz
: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL count_50Khz
: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL count_1Khz
: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_50hz
: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL count_1hz
: STD_LOGIC_VECTOR(4 DOWNTO 0);

2-6

EEET0486

SIGNAL clock_1Mhz_int
: STD_LOGIC;
SIGNAL clock_50Khz_int
: STD_LOGIC;
SIGNAL clock_1Khz_int
: STD_LOGIC;
SIGNAL clock_50hz_int
: STD_LOGIC;
SIGNAL clock_1hz_int
: STD_LOGIC;
BEGIN
-- Divide by 12
PROCESS
BEGIN
WAIT UNTIL clock_12Mhz'EVENT and clock_12Mhz = '1';
IF count_1Mhz < 11 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "0000";
END IF;
IF count_1Mhz < 6 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
END PROCESS;
-- Divide by 20
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
IF count_50Khz /= 9 THEN
count_50Khz <= count_50Khz + 1;
ELSE
count_50khz <= "0000";
clock_50Khz_int <= NOT clock_50Khz_int;
END IF;
END PROCESS;
-- Divide by 50
PROCESS
BEGIN
WAIT UNTIL clock_50khz_int'EVENT and clock_50khz_int = '1';
IF count_1Khz /= 24 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "00000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 20
PROCESS
BEGIN
WAIT UNTIL clock_1khz_int'EVENT and clock_1khz_int = '1';
IF count_50hz /= 9 THEN
count_50hz <= count_50hz + 1;
ELSE
count_50hz <= "0000";
clock_50hz_int <= NOT clock_50hz_int;
END IF;
END PROCESS;
-- Divide by 50
PROCESS
BEGIN
WAIT UNTIL clock_50hz_int'EVENT and clock_50hz_int = '1';
IF count_1hz /= 24 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "00000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
-- Sync all clock outputs back to master clock signal
PROCESS
BEGIN
WAIT UNTIL clock_12Mhz'EVENT and clock_12Mhz = '1';
clock_1Mhz <= clock_1Mhz_int;
clock_50Khz <= clock_50Khz_int;
clock_1Khz <= clock_1Khz_int;

2-7

EEET0486

clock_50hz <= clock_50hz_int;

clock_1hz <= clock_1hz_int;
END PROCESS;
END arch_clock_div;

2. 3 6 2.1 end time = 2.0us grid size = 41.6

ns 2.5

2.5
3. Schematic counter15.gdf Symbol clock_div.gdf Symbol
clock_div.gdf

2-8

EEET0486

2.4 counter15.gdf
1. 2.1-2.3

2.6 counter 15
2. 35 2.1 end time = 20.0us grid size = 41.6 ns

2.7

2-9

EEET0486

2.5 I/O , ByteBlaster

1. MAX+plus II | Floorplan Editor Floorplan Editor Layout | Device View
Layout | Last Complilation Floorplan pin diagram MAX+plus II
2.8

2.8 Foorplan Editor

2. Layout | Current Assignment Floorplan
Floorplan
Copy Assign | Back-Annotate Project
Chips , Pin & Devices OK
3. Floorplan Editor I/O
Pin/Location/Chip
2.9 . Pin/Location/Chip 2.9 .

2 - 10

EEET0486

2.9 .

2.9 . Pin/Location/Chip
g 10 Existing Pin/Location/chip Assignment
Pin 10 8 Change g 8

2 - 11

EEET0486

4. File .acf
File .acf SAVE counter15 .acf MAX + plus II

2.10 Counter15 .acf

5. I/Ocounter15 FLEX10K EPF10K10LC84-3
FPGA
6. (
)
FPGA

2.11 ByteBlaster PC
1. MAX+plus II
(
) IDS
( JTAG IN ) 2.11

2 - 12

EEET0486

2. ByteBlaster
Max + Plus II Programmer
Options | Hardware Setup Hardware Type ByteBlaster OK 2.12
Programmer

2.12 ByteBlaster
3. MAX+plus II | Programmer Programmer
FLEX 10K EPF10K10LC84-3 (
FLEX Only ) MAX+plus II | Programmer Programmer
2.13

2.13 FLEX 10K EPF10K10LC84-3

4. counter15.gdf FLEX10K EPF10K10LC84-3
JTAG Multi-Device JTAG Chain

2.14
2 - 13

EEET0486

5. Multi-device JTAG Chaing Multi - device JTAG Chain Setup

JTAG Device Attributes EPF10K10 OK Select Programming File counter15.sof
OK Device Name Programming File Name ADD 6
( FLEX File .sof )

2.15 FLEX EPF10K10

6. Multi-device JTAG Chain Setup ADD
MAX+plus II Detect JTAG Chain Info
Use Hardware Device OK
Program Configure

2 - 14