D:\cb2re_tb.vhd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -- Vhdl test bench created from schematic C:\Xilinx\bin\test_sch\counter.

sch - Mon Oct 19 12:01:52 2009 --- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vector for the ports of the unit under test. -- Xilinx recommends that these types always be used for the top-level -- I/O of a design in order to guarantee that the testbench will bind -- correctly to the timing (post-route) simulation model. -- 2) To use this template as your testbench, change the filename to any -- name of your choice with the extension .vhd, and use the "Source->Add" -- menu in Project Navigator to import the testbench. Then -- edit the user defined section below, adding code to generate the -- stimulus for your design. -LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY UNISIM; USE UNISIM.Vcomponents.ALL; ENTITY counter_counter_sch_tb IS END counter_counter_sch_tb; ARCHITECTURE behavioral OF counter_counter_sch_tb IS COMPONENT counter PORT( CLK : IN STD_LOGIC; CE : IN STD_LOGIC; CLR : IN STD_LOGIC; CEO : OUT STD_LOGIC; Q0 : OUT STD_LOGIC; Q1 : OUT STD_LOGIC; TC : OUT STD_LOGIC); END COMPONENT; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL CLK CE CLR CEO Q0 Q1 TC : : : : : : : STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;

--DEFINE CLOCK PROCESS VARIABLES constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 0 ns; BEGIN UUT: counter PORT MAP( CLK => CLK, CE => CE, CLR => CLR, CEO => CEO, Q0 => Q0, Q1 => Q1, TC => TC ); ---CLOCK PROCESS PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP Page: 1

D:\cb2re_tb.vhd 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 CLK <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); CLK <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; ---TEST CASE PROCESS -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN CLR <= '1'; WAIT FOR 500 ns; CLR <= '0'; WAIT FOR 500 ns; CE <= '1'; WAIT FOR 10000 ns; WAIT; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section *** END;

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